PURPOSE: To attain ease of handling as a static type, by performing the self- refresh and/or automatic refresh of a dynamic memory cell according to an external refresh control signal.
CONSTITUTION: An edge trigger circuit REG outputs an edge detecting pulse r when any of address signals a0Wa8 is changed. Similarly, an edge trigger circuit CEG outputs a detecting pulse c. An automatic refresh circuit REF consists of an address counter CONT and a timer circuit TM. When a refresh control signal RESH is brought to low with a chip selection signal CS in high level, a signal ref is outputted, an MPX is switched to the counter CONT, the internal address signals a0Wa8 are given to an address decoder R-DCR to attain the automatic refresh with the selecting of one word line. Since the step operation of the counter CONT is performed at each input of the control signal RESH, all the memory cells are refreshed. In keeping the control signal RESH to the low level, a pulse is generated at each prescribed time and continuous refresh is attained.
KAWAMOTO HIROSHI
YASUI NORIMASA
| JPS55150192A | 1980-11-21 | |||
| JPS57109184A | 1982-07-07 |
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