PURPOSE: To obtain a high withstand voltage for the titled transistor using a simple process of manufacture by a method wherein a high specific resistance region is formed in a drain region by performing an ion implantation, and at the end part of a P-N junction surface, the depletion layer provided in an N- type drain region is extended in the direction of the point of a V-groove.

CONSTITUTION: A P type diffusion layer 2 and an N+ type source region 3 are successively formed on an N- substrate 1, and a V-groove 4 reaching said P type diffusion layer 2 is formed through the intermediary of a mask 12. Then, said V-groove 4 is enlarged and the point part of which is extended to the drain region of the N- type substrate 1. Besides, a boron ion implantation is performed in the V-groove 4, where a silicon substrate surface is exposed, through the intermediary of a mask 12, a drive-in process is performed, and then an N-- type drain region 10 having the resistance higher than that of the N- layer 1 is formed, thereby enabling to accomplish a high withstand voltage MOS FET. As the concentration of electric field can be lessened by the expansion of the depletion layer in the N-- layer 10, the surface breakdown generating in the vicinity of the P-N junction located on the side face of the V-groove 4 can be prevented.