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Title:
MANUFACTURE OF MOS INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5916380
Kind Code:
A
Abstract:

PURPOSE: To contrive high density integration by a method wherein, after a first polycrystalline silicon film to be directly contacted to a source or a drain has been formed, a second polycrystalline silicon film to be turned to a gate electrode is formed, thereby unnecessitating to have the matching margin between a contact hole and the polycrystalline silicon film.

CONSTITUTION: A field oxide film 12, an active region 13, a direct contact region 14 and a gate oxide film 15 are formed on an n type Si substrate 11, a hole 16 for direct contact is provided, and a polycrystalline silicon film 17 is formed. Subsequently, after the gate oxide film 15 has been removed, another gate oxide film 18 is formed again. After a second polycrystalline silicon film 19 has been arranged on the gate oxide film 18, a p+ layer 20 is formed by performing an impurity diffusion using a mask. Then, an oxide film 21 is attached, a passivation is performed, contact holes 22a and 22b are provided, an Al adhesion film 23b is provided, wires Y1 and Y2 and a Vcc wire are formed, and the MOS integrated circuit is completed.


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Inventors:
MASUOKA FUJIO
Application Number:
JP5198583A
Publication Date:
January 27, 1984
Filing Date:
March 28, 1983
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/8246; H01L27/112; H01L29/78; (IPC1-7): H01L27/10
Domestic Patent References:
JPS4826479A1973-04-07
JPS4745279A
Attorney, Agent or Firm:
Takehiko Suzue