Title:
METHOD OF PRODUCING SEMICONDUCTOR DEVICE WITH BASE REGION INCLUDING DEEP PART
Document Type and Number:
Japanese Patent JPS5917283
Kind Code:
A
Abstract:
@ A semiconductor device, such as a MOSFET or IGR, is fabricated with a base region having a deep portion for reducing parasitic currents. A wafer is provided having an N type layer on an appropriately doped substrate. A first oxide layer is formed on the wafer, and a refractory electrode layer is deposited on the first oxide layer. A first window is opened in the refractory electrode layer, and then silicon nitride is deposited on the wafer. A second window is opened in the silicon nitride layer, within the first window. A deep P+ base region is diffused into the wafer through the second window, and then a second oxide layer is selectively grown in the second window. The silicon nitride layer is selectively removed, thereby opening a third window, defined by the second window and the second oxide layer situated within the second window. A shallow P base region is diffused into the wafer through the third window, followed by diffusion of a shallow N+ region through the third window. The P-N junction between the N+ region and the deep P+ base region terminates at the surface of the wafer. The second oxide layer is removed, exposing the P-N junction, and the wafer is metallized, thereby implementing an electrical short across the P-N junction.
Inventors:
BANTOBARU JIYAIANTO BARIGA
MAIKURU SUCHIYUAATO ADORAA
MAIKURU SUCHIYUAATO ADORAA
Application Number:
JP11529183A
Publication Date:
January 28, 1984
Filing Date:
June 28, 1983
Export Citation:
Assignee:
GEN ELECTRIC
International Classes:
H01L29/73; H01L21/033; H01L21/331; H01L21/336; H01L29/10; H01L29/739; H01L29/78; (IPC1-7): H01L29/72
Domestic Patent References:
| JPS5726467A | 1982-02-12 | |||
| JPS5610971A | 1981-02-03 | |||
| JPS5736855A | 1982-02-27 |
Attorney, Agent or Firm:
Tokunji Ikunuma