To provide a trench type power semiconductor device which can be manufactured at low cost and has a high breakdown voltage, and to provide a method of manufacturing the same.
On a silicon substrate 2 formed with a p-type base layer 9, a buffer oxide film 8, a silicon nitride film, and a mask material are deposited in this order, and then openings are formed in the laminate, and side walls are formed on the inside surface of the openings. Next, with the laminate and the side walls as a mask, the silicon substrate 2 is etched to form trenches 3. Then, the side walls are removed. With the shoulders 11 of the trenches 3 exposed, thermal oxidation is performed to form a gate oxide film 5 thicker than the buffer oxide film 8 on the internal surface of the trenches 3 as well as round the shoulders 11. Thereafter, trench gate electrodes 6 are embedded in the trenches 3, and the silicon nitride film is removed. Then, by injecting n-type impurity ions into mesa portions 4 via the buffer oxide film 8 to form an n-type emitter layer 10.
MATSUDA NOBORU
JPH09172064A | 1997-06-30 | |||
JP2004111663A | 2004-04-08 | |||
JPH0823092A | 1996-01-23 | |||
JPH10223891A | 1998-08-21 | |||
JPH1174514A | 1999-03-16 | |||
JP2004111661A | 2004-04-08 |
Next Patent: METHOD OF MOUNTING ELECTRONIC COMPONENT