Title:
WAFER POLISHER
Document Type and Number:
Japanese Patent JP3699950
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain the same degree of flatness of a wafer as when a heavy-weight and rigid plate is used, even if a light-weight plate with no rigidity is used.
SOLUTION: By bringing a bottom face 2a of a plate-like spacer 2 and a top face 1a of a plate 1 into surface contact by pressurization by means of a top ring B, the plate-like spacer 2 and the plate 1 are laid on top of each to be integrated into one body. Consequently, insufficient rigidity of the plate 1 can be compensated by the plate-like spacer 2, resulting in an increase in rigidity of the plate 1 into such an extent that a sufficient flatness is achieved for each wafer W or the like.
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Inventors:
Tadashi Imai
Masayoshi Sekizawa
Masayoshi Sekizawa
Application Number:
JP2002289581A
Publication Date:
September 28, 2005
Filing Date:
October 02, 2002
Export Citation:
Assignee:
Naoetsu Electronics Industry Co., Ltd.
International Classes:
B24B37/005; B24B37/04; B24B37/30; H01L21/304; (IPC1-7): H01L21/304; B24B37/00; B24B37/04
Domestic Patent References:
| JP2003273050A | ||||
| JP1216768A |
Attorney, Agent or Firm:
Sadayuki Hosoi
Mitsuo Chonan
Ishiwatari Eibo
Mitsuo Chonan
Ishiwatari Eibo