Title:
WRITE BUFFER OF DATA PROCESSOR
Document Type and Number:
Japanese Patent JP3935286
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain the buffer of small size which operates effectively for burst- mode writing and non-burst mode writing by providing a flag field, which is so set as to indicate which of an address or data value is stored in each line of the write buffer.
SOLUTION: This write buffer with which this data processor is equipped is so constituted as to have plural lines, where addresses or data values are stored and which also has the relative flag field that is so set as to indicate that the respective lines have which of the address or data value. For example, bits 0 to 31 of each line 310 of the write buffer are so reserved as to store an address or data value. Furthermore, bits 32 to 35 are so reserved as to store either of 4-bit control data relating to the address stored in the line and a 4-bit data mask relating to the data value stored in the line.
Inventors:
David Walter Flynn
Application Number:
JP8029099A
Publication Date:
June 20, 2007
Filing Date:
March 24, 1999
Export Citation:
Assignee:
RM Limited
International Classes:
G06F12/00; G06F5/12; G06F12/02; G06F12/04; G06F12/08; G06F12/0879; G06F12/10; G06F12/1045; G06F13/42; (IPC1-7): G06F12/00; G06F5/06; G06F12/08
Domestic Patent References:
| JP2250138A | ||||
| JP5158787A | ||||
| JP5079651U |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu