Title:
Dynamic pipeline for graphics processing
Document Type and Number:
Japanese Patent JP6309696
Kind Code:
B2
Abstract:
This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.
Inventors:
Li, Lian
Gruber, Andrew Ivan
Jao, Guo Fan
Ji, Jenyu
Pittaries, Gregory Steve
Nolan, Scott William
Gruber, Andrew Ivan
Jao, Guo Fan
Ji, Jenyu
Pittaries, Gregory Steve
Nolan, Scott William
Application Number:
JP2017524392A
Publication Date:
April 11, 2018
Filing Date:
October 15, 2015
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06T15/00; G06F9/38; G06T1/20
Domestic Patent References:
| JP2007328774A | ||||
| JP2007526585A |
Foreign References:
| US5798770 |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada