Title:
ACTIVATION SIGNAL DETECTING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2007/086255
Kind Code:
A1
Abstract:
The variation of the threshold value of a diode-connected transistor is compensated for so as to maintain a constant rectification efficiency of a rectifying circuit, thereby performing a stable activation signal detection. A constant voltage is applied to a DC bias terminal (103) of a cascaded half-wave doubled-voltage rectifying circuit (comprising MOS transistors M1-M4 and capacitors C1-C4) constituting a rectifying circuit. Another voltage is applied to a DC bias terminal (104) of a cascaded half-wave doubled-voltage rectifying circuit (comprising MOS transistors M5-M8 and capacitors C5-C8) constituting a bias circuit. That other voltage is obtained by adding a variation (ΔVt) of the threshold voltage of a MOS transistor to the constant voltage applied to the DC bias terminal (103).
Inventors:
YAMASE TOMOYUKI (JP)
MAEDA TADASHI (JP)
MAEDA TADASHI (JP)
Application Number:
PCT/JP2007/050191
Publication Date:
August 02, 2007
Filing Date:
January 11, 2007
Export Citation:
Assignee:
NEC CORP (JP)
YAMASE TOMOYUKI (JP)
MAEDA TADASHI (JP)
YAMASE TOMOYUKI (JP)
MAEDA TADASHI (JP)
International Classes:
H03D1/18; H02M7/10; H03K17/13
Foreign References:
| JP2006319549A | 2006-11-24 | |||
| JP2004194301A | 2004-07-08 |
Other References:
DICKSON J.P. ET AL.: "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 11, no. 3, 1976, pages 374 - 378, XP009035607
Attorney, Agent or Firm:
MIYAZAKI, Teruo et al. (16th Kowa Bldg. 9-20, Akasaka 1-chom, Minato-ku Tokyo 52, JP)
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