ACTIVE-MATRIX DISPLAY

WIPO Patent Application WO/2005/106834

A1

A display is disclosed which comprises a plurality of scanning lines (Wscan, Escan) which are selected sequentially, a plurality of data lines (Data) to which a write current (Idata) according to luminance information is supplied according to selection of the scanning lines, and a plurality of pixels (PX) arranged on their intersections. Each pixel comprises a light-emitting device (OLED), a drive transistor (TFT4), a capacitor (C) which is connected to the gate (Nd) of the drive transistor and stores write date, a first transistor (TFT1) which conducts during a write period when the scanning line is scanned and connects the date line and the drain of the drive transistor, and a second transistor (TFT2) which conducts during the write period and short-circuits the gate and drain of the drive transistor. This structure enables to drive the light-emitting device with a drive current which is equivalent to the write current without being affected by variations in transistor characteristics.

JP5631130	Organic EL display device
JPH0363691	GRADATION CONTROLLER FOR EL DISPLAY DEVICE
JPS63167396	IMAGE DISPLAY

ISHIZUKA ATSUO (JP)
YAMAGUCHI HISASHI (JP)
HASHIMOTO YASUNOBU (JP)

PCT/JP2004/006352

November 10, 2005

April 30, 2004

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FUJITSU LTD (JP)
ISHIZUKA ATSUO (JP)
YAMAGUCHI HISASHI (JP)
HASHIMOTO YASUNOBU (JP)

G09G3/30; G09G3/32; (IPC1-7): G09G3/30

WO2001006484A1

2001-01-25

JP2002517806A	2002-06-18
JP2004069816A	2004-03-04
JP2002514320A	2002-05-14
JP2003150118A	2003-05-23
JP2001060076A	2001-03-06

Nakajima, Jun (NAKAJIMA & KATO Seventh Floor, HK-Shinjuku Bldg., 3-17, Shinjuku 4-chom, Shinjuku-ku Tokyo 22, JP)

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