SIGNALS FOR COMPONENT TELEVISION VIDEO SIGNAL RECEPTION

The present invention relates ^* to a system for transmitting and/or receiving television video signals in component form, which components have been time compressed and placed sequentially so as to occupy, together with the necessary sync and clamping signals, a period substantially identical to the existing line period e.g. approximately 64 IAS.

It has already been proposed to compress the video component signals to such an extent that an audio signal can be included either before or after the video com¬ ponent signal, within the line period. It is preferred that this audio signal takes the form of a digital signal placed before the video components signals. Further, it has been proposed to add to this digital signal a predetermined sequence of digits for use as either a sound or line sync signal.

We now propose that a plurality of predetermined digital sequences be used, each in a different line, from which both line and field syncs may be derived in a receiving apparatus.

Preferably, there will be just two predetermined sequences which will alternate line by line for the bulk of one field but one of the sequences will be repeated for a plurality of lines just prior to the end of one field while the other of the sequences will

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be repeated for a plurality of lines at the beginning of the next field. The sequences will then alternate as before.

The present invention provides apparatus for deriving synchronisation signals from a received television signal which has a sequence of a plurality of different digital words; each is a respective one of a plurality of lines as synchronisation signals, comprising means for generating a ^" first sxgnal indicative of detection of one of the digital words, means for generating a further signal indicative of detection of a further digital word, means for evaluating the first and further signals to determine the sequence and timing of the first and further signals whereby to generate a signal indicative of synchronisation signal acquisition for initiating generating of receiver sync signals at line frequency.

In order that the present invention be more readily understood, reference will now be made to the accompanying drawings, in which:-

Figure 1 shows diagrammatically a multiplexed component signal showing the time division multiplex between the component parts thereof;

Figure 2 shows diagrammatically a frame of C-MAC signals offset by _ frame and _ line as well as the multiple timing of each line in the frame .

Figure 3 shows a block diagram of a receiver incorporating the present invention;

Figure 4 shows a state diagram to explain the operation of the circuit shown in Figure 3-

Figure 5 shows a block diagram of a further receiver incorporating the present invention; and

Figures 6A and 6B show state diagrams to explain the operation of the circuit shown in Figure 5-

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The Multiplex Analogue Components (MAC) system for whom television signal transmission replaces the colour subcarrier coding of NTSC, PAL and SECAM with a single method of time compression. The conventional

5 studio colour coder is replaced by a MAC coder which separately time compresses each active picture line (52 its nominally) of luminance (Y) and chrominance (alternate lines contain U and V). By using either charge-coupled devices (ie CCDs) or digital storage, these compressed 10 lμminance and chrominance components can be placed in sequence within the 64 ks of each line period. Conven¬ tional sync pulses, designed for receiver technology of 30 years ago, are no longer required and are replaced by other synchronisation information within the waveform. 15 The colour subcarrier burst is no longer required, and any timing information required for future developments such as extended definition receivers can be derived from the video and sound/data signals.

This time compression results in a proportionate 20 increase in the bandwidth required to pass the signal. The extra bandwidth of the time-compressed baseband signal can be accommodated within a satellite FM transmission channel, since the spectral width of the FM signal is a function of both the frequency and 25 amplitude of the baseband signals.

In one version of MAC known as C-MAC, the synchronisation, sound and data signals are digitally modulated onto the carrier in the line-blanking interval of the MAC signal, giving an overall time division 30 multiplex of the RF carrier as shown in Fig 1. The complete absence of high frequency sub-carriers either for colour or for sound allows the bandwidth of the baseband signals to be increased with the upper limit set by interference constraints. The use of large 35 amounts of pre- and de-emphasis to reduce distortion on

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subcarriers becomes unnecessary. As a result, the pre- and de-emphasis can be reduced to a level to give optimum noise and interference performance.

Time division multiplexing of the digital synchronisation, sound and data with the analogue video signal is carried out at an intermediate frequency, switching between digital modulation for the synch¬ ronisation, sound and data, and frequency modulation for the chrominance and luminance as shown in Figure 1. Such switching is carried our without discontinuity of phase in the main carrier.

The internationally agreed studio standard for component-coded digital video has been established with sampling frequencies 13-SMHz for luminance and 6.75MHz for chrominance. Luminance compression of 1.5-1 and chrominance compression of 3=1 which are used for C-MAC mean that after compression the effective sampling frequencies for both luminance and chrominance are 20.25MHz. For convenience of generation and recovery, the same data rate is chosen for the sound signal. In defining the waveform, it is convenient to divide the 64 usec video line into 1296 time slots or 'samples' based on integer periods of 49-4 nsec (l/20.25MHz) which are shown in Fig. 2 which shows the format of a C-MAC signal offset by _ line and _ frame.

On this basis, the line is broken into the three component parts of the time division multiplex as shown in Table I.

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TABLE I

Number of bits/samples Total duration Function

8 bits 0.40 usec digital synchronisatio

186 bits 9.l8 usec digital sound/ data

1102 samples 54.42 usec analogue video

(MAC)

Synchronisation

Synchronisation signals for C-MAC are: i) video line sync ii) video frame sync iii) U/V identification iv) Extended-definition synchronisation v) Sound synchronisation

i) Video line sync : This is available in two ways

a) From the digital burst. The first 8 bits of the digital burst carry synchronisation information, consisting of a run-in bit for differential detection and seven bits for the synchronising words . There are two line synchronising words W.. and W„ which are sent on alternate lines. Their relative positions are inverted once every frame to provide a frame reference as shown in Table 2 belbw.

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TABLE 2

Frame Number Line Number Sync Word Frame Number Line Niαmber Sync Word

Frame Boundary

etc etc etc etc

15 The two line sync words are defined as: W- = 1 0001101 w: = o liiooio

Signalling bits. On 20 lines of each frame, the line sync word W„ is replaced with a 7 bit word which may be used for signalling purposes.

20

These lines are as follows :

Even frames - line 26, 58, 74, 90, 152, 182, 198, 216,

276, 308, 324, 340, 400, 432, 458, 466, 526, 558, 574, 25 590.

Odd frames - line 27, 59, 75, 91, 153, 183, 199, 217,

277, 309, 325, 341, 401, 433, 459, 467, 527, 559, 575, 591.

30

Even and odd frames are defined in Table 2,

Line syncs may also be derived by detecting a unique frame sync word placed in line 625 as shown in 35 Fig. 2 and using this to lock an oscillator running at line rate.

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b) From the video waveform. This is provided by the exact spacing of edges 'e' and 'h' of Figure (2). Edges which may occur in pictures at the same spacing are eliminated by the field sync lines in which there is no picture information. The amplitude of the sync edges (0.5v) allows for rugged sync separation.

ϋ) Video field sync : This is available in two ways

a) From the digital burst. The first 8 bits of the digital burst provide not only the line syncs, but by inversion of the relative positions of the words once every frame a rugged frame sync is provided as shown in Table 2 above. Alternatively, a distinct and unique field sync word can be inserted in line 625 as shown in Fig. 2.

b) From the video waveform. Line 1 of the video consists of the waveform shown in Figure 9 while line 313 contains the wave¬ form shown in Figure 10. This provides a very rugged method of frame synchronis¬ ation, since these lines are clearly distinguishable from any other line of each frame. The waveform of line 1 corresponds to Y=-0.15 and U=-0.65, while that of line 313 corresponds to Y=-1.15 and

U=+0.65 (V=0, ie these are lines of U chrominance). These values are outside the permitted RGB limits for picture information. Frame sync separation, field identification, line count and indeed line sync can be established from these lines.

iii) U/V identification. The U/V identification is derived directly by line count from the frame sync derived in 'b ¹ above. The odd lines of the frame carry U information and the even lines carry V information.

iv) Extended definition synchronisation. For. extended processing which may be introduced in the future, the 20.25 MHz clock required is recovered form the sound data burst.

v) Sound synchronisation. Sound synchronisation is obtained by obtaining line and frame synchronisation from the digital burst which then provides total synchronisation of the sound/data channel.

Turning now to the generation of sync signals at the receiver from the C-MAC waveform shown in Fig. 1, it will be recalled that the timings for the MAC receiver are derived from a line-locked 20.25MHz clock. This has a period of ^>49 S, and there are 1296 clock samples per television line. As timing information for clock regeneration is derived from the data burst, it can be seen that timing information is only present for 15 of the time.

The synchronisation period consists of an 8-bit sequence transmitted at the start of each data burst. Of this the first bit is a run-in bit, and without synchronisation detection can be considered to be of no useful value. The other seven bits contain both the horizontal and vertical sync information in the format shown below.

From Table 2 it will be appreciated that a line sync can be considered to consist of either the word pair

A frame sync will then consist of the sequences . W ₁ W ₂ W ₂ or W ₂ W ₂ W W reversing a W W ₂ pair at the frame boundary.

The choice of words for W , W ₂ is governed solely by the desired behaviour of the system under conditions of noise.

Both W. and W ₂ should be chosen to have smallest possible correlation with shifted versions of themselves to prevent false lock occuring. Based on computer search, the seven bit sequence 0001101 has been found to be optimum with regard to shifted versions of itself and also simulation of the sequence by video/data and noise.

In order to prevent confusion between W_. and W ₂ occurring in the reciever, a large Hamming distance between the two is desirable, and hence W ₂ was chosen to be 1110010.

To keep the average D.C. level to _ , the run in bit was chosen to be 1 for W.. and 0 for W ₂ .

Receiver Sync Detection

Although only seven bits of sync information are sent on each line, the sequence of W. W ₂ allows an effective line sync word length of 14 bits and an effective frame sync word length of 28 bits to be used. This is shown below:-

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Line Sync Word Line Sync Sequence Frame Sync Sequence

A line sync is therefore present on every line and a frame sync once a frame.

On the lines marked -"- a line sync is not detected due to the W W ₂ pair inversion to signal a frame sync. The ability of the system to stay in lock is not affected because the line sync detection is inhibited during these 2 lines once a frame lock is established.

The line marked ! contains a valid line sync, but the W ₁ W ₂ pair sequence is inverted. This can be used as a less rugged form of frame sync if desired for a simpler receiver and is indicated in Fig. 2.

A block diagram of the receiver detector is shown below in Figure 3, and a brief description of the operation follows.

A phase locked loop (not shown) recovers the 20.25MHz clock from the incoming data stream in a con¬ ventional manner. Even when not locked, the oscilllator of the phase locked loop is running at a nominal 20.25MHz and so there is only scale difference in phase between the incoming data stream and the oscillator which results in long period of in phase running of the oscillator in facilitate lock-up.

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The input serial data stream is then converted to an n bit wide parallel data stream by a serial to parallel converter 20, where n is the width of the line sync (ie n = 7) • This is processed by a sync word recognition circuit 21 which converts the continuous 20Mb/s data sream to a continuous error pattern. That is, the output represents the number of bits that the input is away from W ₁ . For example, in the case of W ₂ this is the Hamming distance, or 7« Line Sync Extraction

Since ^ . = ^ ₂ , by inverting the present sample and summing this with the same sample from the previous line, a maximum will occur with the line pair W.. W ₂ and a minimum with the pair W ₂ W_.. By comparing these with and (the number of errors allowed in a sync word pair before a detection is deemed to be missed) line syncs may be extracted (along with other false detections due to random data) from the input data stream.

The figure -2-jfc, may be used as a measure of the BER for the channel.

This operation is achieved by means of an inverter 22 which inverts the present sample and feeds it to one input of an adder 23 whose other input is supplied with the output from a line delay circuit 24. The output of the adder 23 is fed to a comparing circuit 25 where the 4 bit output of the adder 23 is compared with predetermined maximum and minimum numbers of errors and if the level of the output of the adder 23 falls between the maximum and minimum numbers of errors a line sync detection signal is generated.

A frame sync signal could also be extracted from the circuit 25 by detection when minimum and maximum signals are produced.

Frame Sync Extraction

This is preferably performed in a manner similar to line syncs with one important difference. The uninverted present sample is in this case summed with the same sample from the previous line in an adder 27- This gives a minimum for W. . and a maximum for the sequence W ₂ W ₂ . This result is delayed by two lines in a delay circuit 28 which comprises a 2 x 4 bit 2 line gated latch and added to the inverted undelayed signal 0 in an adder 30.

Again this result has a minimum for W ₂ W ₂ . W. and a maximum for . W W ₂ W ₂ . By using a comparison circuit 31 for comparing this result with the number of errors allowable before a detection is not signalled, frame syncs may be detected. 5

The significant difference between frame sync and line sync extraction is the two line _. delay circuit 28. This is simply a two element shift register clocked with the regenerated line sync . 0 Once line lock has been established, the precise horizontal position of the frame sync within one of only 625 possible positions. It is effectively 'pointed to' by the line syncs. Hence the frame sync is made much more robust. This contrasts with a system using a ς frame sync word only ie where the frame sync may be in one of 625 x 1296 locations. Acquisition of Lock

The previous section described in the recovery of the sync pulses. False sync pulses may also be _Q generated by the random data in the channel, or by a particular arrangement of video signals. Therefore some sort of discrimination is required to extract the true syncs from any possible misdetections.

The process by which lock is acquired is governed 5 by the state diagram shown in Fig. 4«

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In the initial state any detection of the sync word is accepted, and a counter connected to the output of the comparing circuit 25 is moved to state (^ .

If this detection is not the sync word then the counter returns to state (~ ) .

If it is the sync word, the counter progresses to - state 4 and the system has aquired lock.

Once line syncs have been acquired, the position of the data burst is known with certainty, and the clock recovery PLL is gated to prevent spurious signals (eg video) outside the burst increasing the amount of jitter on the clock.

After 16 consecutive mis-detections the system reverts to state (_^ and has lost lock. The state diagram is the same for line and frame syncs, but acquisition of frame sync is not initiated until line lock is acquired when the position of frame sync can be indicated by line syncs.

The figures in this diagram allow lock to be acquired and held at a C/N of OdB in the UKIBA C-MAC system. This has been confirmed by experimental results.

Sync acquisition is thus by two distinct processes : 1) Detection of line and frame sync. 2) Lock acquisition and digital flywheeling. Clock recovery is gated as soon as line lock is established (3 lines) thereby reducing clock jitter at low C/N. The clock has only to run ungated for 3 lines as opposed to running ungated accurately for at least one frame.

Figure 5 shows a block diagram of a part of a receiver concentrating on sync detection and acquisition which differs from that shown in Fig. 3 in that it is much more simple and easy to instruct. The previously described receiver required a

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fairly substantial amount of hardware, mostly running at the 20.25Mb/s clock rate.

The receiver shown in Figure 5 and described below has a considerably reduced amount of logic running at 20.25MHz and in particular contains no line store. The same reference numerals are used for the same parts as in Fig. 3>

In ^' Fig. 5, serial incoming data is inverted as before in a circuit 40 to produce a 3-bit error word. A line sync acquisition and flywheel and state counter circuit 41 receives an input from a word detection circuit each time a _j or W ₂ word is detected by a word detection circuit 4 connected to the output of the circuit 40. It also receives the line sync detection signal generated by the comparing circuit 25- The counter circuit 41 generates a number of outputs among which is a line rate clock signal which is fed to a 3-bit latch 43 which replaces the line delay circuit 24 of Fig. 3. The counter circuit 41 also acts as a reference signal generator for generating reference signals for application to a word detector and adaptive error control circuit 44j the reference signal being used to select the type of detection and number of errors tolerated by the detector 2 and the comparing circuit 25-

For frame sync detection, the arrangement is as described in relation to Fig. 3 with the 2 line delay 28 responsive to the line rate clock now generated by the counter circuit 1 • Adaptive error control is achieved using a frame sync flywheel and acquisition circuit 46 and an error control circuit 47 which operates in a similar manner to the corresponding circuits described in relation to line sync detector.

The process of line sync acquisition will now be described with reference to Fig. 5 and Figs. 6A and 6B.

Initially search for W, (only W _j detections are output from a comparator on the output of the serial to error converter 40, allowing n errors).

If W. is found, the counter circuit 41 moves to state (Figure 3A) and searches for an occurrence of W ₂ precisely 1296 clock cycles (1 line) later. This is also output form the word recognition circuit 42 since _j = W ₂ .

If W ₂ is not found, the counter circuit 41 reverts to state 0 (Figure 3A) and continues to search for another occurrence of ..

If W ₂ is found, then the probability of having found a line sync pair is quite high, and the receiver switches over to the sum of errors mode of the previous receiver, except that in this case, the line store is replaced by 3-bit latch 43 clocked by the assumed position of line sync found from the separate W. and W ₂ detections.

The counter circuit 41 is now at state 2 in (Figure 3A If the syncs were correctly indentified then the conventional locking procedure will be followed and the counter circuit 41 will sit at state 5 (in Figure 3 ) and the receiver will have acquired line lock and a line sync output will be generated by the circuit 41 •

At this point, the search for frame lock is initiated and when frame sync is acquired a frame sync output is generated from the circuit 46.

Frame syncs are detected using a 2 latch double line delay as before, and frame lock is also acquired as before. In both line and frame cases, increasing BER will increase the probability of sync detection being missed and hence the counters 41 and 46 will advance from the in lock state. After a number of counts from these states (n Λ and n -^ ) the number of errors tolerated before a sync word detection is missed is increased

using the circuits 44 and 47, therefore giving a greater probability of detecting a sync word in the presence of noise. Once a word is detected and the system returns to the in lock state, the number of errors tolerated is reduced to the original level. Once frame lock is lost, re-acquisition takes place as normal.

Once line lock is lost, instead of reverting to state zero, the counter circuit 41 reverts to state 2. There are two reasons for loss of line lock - loss of signal, or m consecutive mis-detections due to noise.

In the former case the counter circuit 1 will return to state 0 via state 2.

In the latter case, if sync words are detected there is the possibility of re-acquiring lock whilst still running in the two word mode thereby considerably reducing the interruption to sound and vision caused by loss of lock.

Adaptive error tolerance on either or both line and frame sync detection, allows sync extraction in the presence of a greater amount of noise (or higher BER) . The arrangement shown in Fig. 5 has an increased initial lock up time with respect to that of Fig. 3- This is increased by an average of 1 _ lines in low BER conditions o approximately 40 lines at a BER of 10 ^" .

Although not shown in Figure 3, it will be appreciated that a modified version of the counter circuit 41 in Figure 5 will be used and that adaptive error control of the circuit 25 and/or circuit 31 is possible.

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