Title:
BACK-GATE FIELD-EFFECT TRANSISTORS AND METHODS FOR MAKING THE SAME
Document Type and Number:
WIPO Patent Application WO/2019/148170
Kind Code:
A3
Abstract:
A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (Lԍ) or contact length (Lc). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6x improvement to EDP compared to top-gate CNFETs.
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Inventors:
SHULAKER MAX (US)
SRIMANI TATHAGATA (US)
FULLER SAMUEL (US)
STEIN YOSI (US)
MURPHY DENIS (US)
SRIMANI TATHAGATA (US)
FULLER SAMUEL (US)
STEIN YOSI (US)
MURPHY DENIS (US)
Application Number:
PCT/US2019/015595
Publication Date:
April 16, 2020
Filing Date:
January 29, 2019
Export Citation:
Assignee:
MASSACHUSETTS INST TECHNOLOGY (US)
SHULAKER MAX (US)
SRIMANI TATHAGATA (US)
FULLER SAMUEL (US)
STEIN YOSI (US)
MURPHY DENIS (US)
SHULAKER MAX (US)
SRIMANI TATHAGATA (US)
FULLER SAMUEL (US)
STEIN YOSI (US)
MURPHY DENIS (US)
International Classes:
H01L21/02; H01L29/02; H01L29/732
Domestic Patent References:
WO2017001406A2 | 2017-01-05 |
Foreign References:
US8785911B2 | 2014-07-22 | |||
US9209288B2 | 2015-12-08 | |||
US8557659B2 | 2013-10-15 | |||
US20170179283A1 | 2017-06-22 | |||
US6191724B1 | 2001-02-20 | |||
US6462929B2 | 2002-10-08 | |||
EP0190070B1 | 1992-08-26 |
Attorney, Agent or Firm:
COLICE, Christopher Max et al. (US)
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