Title:
BITLINE MULTI-LEVEL VOLTAGE SENSING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/022298
Kind Code:
A1
Abstract:
The present invention relates to a bitline multi-level voltage sensing circuit for a multi-bit operation of a DRAM including a memory cell that stores data by an operation of a wordline and a bitline, the bitline multi-level voltage sensing circuit comprising: an operational amplifier having a non-inverting input terminal coupled to a precharging voltage line and an inverting input terminal coupled to a bitline through a first switch enabled by a wordline signal; a feedback capacitor formed between an output terminal of the operational amplifier and an inverting input terminal of the operational amplifier; a second switch formed in parallel with the feedback capacitor between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier and enabled by a precharging signal; and an analog-to-digital converter that converts an output voltage of the output terminal of the operational amplifier into a digital signal.
Inventors:
CHO SEONG HWAN (KR)
LEE GI WOO (KR)
LEE GI WOO (KR)
Application Number:
PCT/KR2021/016738
Publication Date:
February 23, 2023
Filing Date:
November 16, 2021
Export Citation:
Assignee:
KOREA ADVANCED INST SCI & TECH (KR)
International Classes:
G11C11/4091; G11C11/408; G11C11/4094; H03M1/12
Foreign References:
| US20200233482A1 | 2020-07-23 | |||
| KR20100049926A | 2010-05-13 | |||
| KR20110026812A | 2011-03-16 | |||
| KR20090072870A | 2009-07-02 | |||
| KR20210108384A | 2021-08-17 |
Other References:
JIANG ZHEWEI; YIN SHIHUI; SEO JAE-SUN; SEOK MINGOO: "C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 55, no. 7, 1 July 2020 (2020-07-01), USA, pages 1888 - 1897, XP011795573, ISSN: 0018-9200, DOI: 10.1109/JSSC.2020.2992886
Attorney, Agent or Firm:
SU INTELLECTUAL PROPERTY (KR)
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