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Patent Searching and Data


Title:
BONDING STRUCTURE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2021/168953
Kind Code:
A1
Abstract:
A bonding structure and a manufacturing method therefor. A wafer stack is formed by bonding multiple layers of wafers in sequence. Chip stacks are arranged on the wafer stack in an array. The chip stacks each comprise multiple layers of chips that are bonded in sequence. An electrical lead-out structure is formed in each chip stack. The electrical performance of all of the chip stacks can be tested by forming a full lead-out structure that is electrically connected to an interconnection layer in each layer of chips in the chip stacks, the electrical performance of some layers of chips in the chip stacks can be tested by some lead-out structures in some electrically connected layers of chips, and/or the electrical performance of a single layer of chips in the chip stacks can be tested by means of a single lead-out structure that is electrically connected to an interconnection layer in the single layer of chips, thereby testing the electrical performance of a single layer or multiple layers of chips in the chip stacks, thus obtaining the specific position of a failed chip.

Inventors:
ZHAN DI (CN)
HU XING (CN)
LIU TIANJIAN (CN)
HU SHENG (CN)
Application Number:
PCT/CN2020/080806
Publication Date:
September 02, 2021
Filing Date:
March 24, 2020
Export Citation:
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Assignee:
WUHAN XINXIN SEMICONDUCTOR MFG (CN)
International Classes:
H01L25/065; H01L21/98
Foreign References:
CN109755190A2019-05-14
CN101542701A2009-09-23
US20030164551A12003-09-04
CN104851875A2015-08-19
CN105140142A2015-12-09
Attorney, Agent or Firm:
UNITALEN ATTORNEYS AT LAW (CN)
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