Title:
CHIP FUSE AND METHOD OF MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2010/116553
Kind Code:
A1
Abstract:
Provided is a chip fuse which maintains the same level of fusing characteristics as conventional ones and is highly safe in that an increase in an internal resistance value can be sufficiently decreased. The chip fuse comprises an insulating substrate provided with a glaze layer, a fuse film provided with a narrow fusing portion provided on the glaze layer, surface electrodes formed at both end portions of the upper surface of the fuse film, a glass film provided on at least the upper surface of the fuse film, an overcoat film consisting of a resin layer which covers the glass film and the fuse film provided with the glass film, and end surface electrodes, and has a structure in which the glass film is provided in contact with the portion of the upper surface of the fuse film on which no surface electrode is formed and the overcoat film is provided in contact with the side surfaces of the fuse film.
Inventors:
HIRAIZUMI ATSUSHI (JP)
HIRANO TATSUKI (JP)
NAKANISHI KOJI (JP)
HIRANO TATSUKI (JP)
NAKANISHI KOJI (JP)
Application Number:
PCT/JP2009/067700
Publication Date:
October 14, 2010
Filing Date:
October 13, 2009
Export Citation:
Assignee:
KAMAYA ELECTRIC CO LTD (JP)
HIRAIZUMI ATSUSHI (JP)
HIRANO TATSUKI (JP)
NAKANISHI KOJI (JP)
HIRAIZUMI ATSUSHI (JP)
HIRANO TATSUKI (JP)
NAKANISHI KOJI (JP)
International Classes:
H01H85/048; H01H69/02; H01H85/10; H01H85/17
Foreign References:
| JPH1050191A | 1998-02-20 | |||
| JPH09129115A | 1997-05-16 | |||
| JPH08102244A | 1996-04-16 |
Attorney, Agent or Firm:
SAKAI Hajime et al. (JP)
Sakai 1 (JP)
Sakai 1 (JP)
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