CHIP STACK PACKAGING STRUCTURE, PACKAGING METHOD THEREOF AND ELECTRONIC DEVICE

WIPO Patent Application WO/2021/081943

A1

A chip stack packaging structure and a packaging method thereof, and an electronic device, related to the technical field of electronics, and used to solve the problem of partial delamination in large-dimension packaging structures. A chip stack packaging structure (100) comprises: a redistribution layer (10); multiple bare chips (20) disposed at intervals, there being a first gap (N1) between adjacent bare chips (20); a solder assembly (30) positioned between the redistribution layer (10) and the bare chips (20), used to support the bare chips (20) and implementing an electrical connection between the bare chips (20) and the redistribution layer (10); a separation wall (85) disposed at a side of the redistribution layer (10) facing the bare chips (20), and at a position corresponding to the first gap (N1); a first underfill layer (40), filling in an area enclosed by the redistribution layer (10), the bare chips (20) and the separation wall (85), and packaging the solder assembly (30); a plastic sealing layer (50) covering the bare chips (20) and filling in the first gap (N1).

TSAI CHUNGHSUAN (CN)
ZHANG CHI (CN)
TAO JUNLEI (CN)
ZHAO NAN (CN)
CHIANG SHANGHSUAN (CN)

PCT/CN2019/114866

May 06, 2021

October 31, 2019

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HUAWEI TECH CO LTD (CN)

H01L21/60; H01L23/488

JP2017005175A	2017-01-05
CN109599380A	2019-04-09
CN106816421A	2017-06-09
CN106887393A	2017-06-23
CN102543968A	2012-07-04
CN208655611U	2019-03-26

BEIJING ZBSD PATENT & TRADEMARK AGENT LTD. (CN)

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