Title:
COMMAND DECODING CIRCUIT AND METHOD THEREOF, AND SEMICONDUCTOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/060317
Kind Code:
A1
Abstract:
Embodiments of the present disclosure provide a command decoding circuit and a method thereof, and a semiconductor memory. The command decoding circuit comprises: a clock processing module, which is configured to receive an initial clock signal, perform frequency division and phase division on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; a command sampling module, which is configured to receive a command address signal, sample the command address signal by using the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, and output a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal; and a decoding module, which is configured to decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal on the basis of the first clock signal and the third clock signal, and output a target decoded signal.
Inventors:
GAO ENPENG (CN)
Application Number:
PCT/CN2022/123984
Publication Date:
March 28, 2024
Filing Date:
October 09, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/413
Foreign References:
| CN109903793A | 2019-06-18 | |||
| CN107844439A | 2018-03-27 | |||
| US20210405927A1 | 2021-12-30 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
Download PDF:
Previous Patent: BUILT-IN SELF-TEST METHOD AND DEVICE
Next Patent: SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
Next Patent: SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR