Title:
COMPLEMENTARY SWITCH ELEMENT
Document Type and Number:
WIPO Patent Application WO/2020/138168
Kind Code:
A1
Abstract:
This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode through which an electric field is applied to the interface between the group IV semiconductor substrate and the nanowire. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.
Inventors:
TOMIOKA KATSUHIRO (JP)
Application Number:
PCT/JP2019/050823
Publication Date:
July 02, 2020
Filing Date:
December 25, 2019
Export Citation:
Assignee:
UNIV HOKKAIDO NAT UNIV CORP (JP)
International Classes:
H01L27/092; B82Y10/00; H01L21/336; H01L21/337; H01L21/338; H01L21/8238; H01L29/78; H01L29/808; H01L29/812
Domestic Patent References:
| WO2017057329A1 | 2017-04-06 | |||
| WO2015022777A1 | 2015-02-19 | |||
| WO2011040012A1 | 2011-04-07 | |||
| WO2015064094A1 | 2015-05-07 | |||
| WO2011040012A1 | 2011-04-07 |
Foreign References:
| US20160293739A1 | 2016-10-06 | |||
| US20160172246A1 | 2016-06-16 | |||
| JP2011238909A | 2011-11-24 | |||
| JP2014525144A | 2014-09-25 | |||
| JP2018247228A | 2018-12-28 |
Other References:
BHUWALKA, K. K.SCHULZE, J.EISELE, I.: "Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 52, no. 5, May 2005 (2005-05-01), pages 909 - 917, XP011130966, DOI: 10.1109/TED.2005.846318
BHUWALKA, K. K.SCHULZE, J.EISELE, I.: "A simulation approach to optimize the electrical parameters of a vertical tunnel FET", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 52, no. 7, July 2005 (2005-07-01), pages 1541 - 1547, XP011135503, DOI: 10.1109/TED.2005.850618
See also references of EP 3905327A4
BHUWALKA, K. K.SCHULZE, J.EISELE, I.: "A simulation approach to optimize the electrical parameters of a vertical tunnel FET", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 52, no. 7, July 2005 (2005-07-01), pages 1541 - 1547, XP011135503, DOI: 10.1109/TED.2005.850618
See also references of EP 3905327A4
Attorney, Agent or Firm:
WASHIDA & ASSOCIATES (JP)
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