Title:
COMPUTATION PROCESSING DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/024755
Kind Code:
A1
Abstract:
The present disclosure is a computation processing device for a first matrix a = [a0, a1, a2, …, aM-1] and a second matrix b = [b0, b1, b2, …, bM-1] that are M by N dimensional arrays of M N-dimensional column vectors. When a calculation for determining a third matrix x = [x0, x1, x2, …, xM-1] is obtained by x = aTb, the product of the matrixes, the third matrix x being an M by M dimensional array of M M-dimensional column vectors including dot products for combinations of all column vectors belonging to the first matrix and the second matrix, in each of M computation units 11 serving as constitutional minimum units of a computation processing device 10, a pair of column vectors [am, bm] of the first matrix a = [a0, a1, a2, …, aM-1] and the second matrix b = [b0, b1, b2, …, bM-1] is stored in the m-th computation unit, the M computation units are connected via a series network 14, array data of a N-dimensional column vector bm is transmitted from any one of the computation units and is sequentially propagated through the adjacent downstream computation units, the dot product of the column vectors b0, b1, b2, …, and bM-1 of the second matrix and am stored in the computation unit, that is, an M-dimensional column vector xm = [am·b0, am·b1, am·b2, …, am·bM-1]T that constitutes the array part of the M by M dimensional third matrix is calculated in the m-th computation unit, and the M-dimensional column vector xm is stored in the m-th computation unit, wherein am, bm, and xm are column vectors stored as arrays in the computation unit.
Inventors:
OUCHI SHINICHI (JP)
Application Number:
PCT/JP2023/027078
Publication Date:
February 01, 2024
Filing Date:
July 24, 2023
Export Citation:
Assignee:
AIST (JP)
International Classes:
G06F17/16; G06N3/063
Foreign References:
| JPH04330828A | 1992-11-18 | |||
| JPH0773161A | 1995-03-17 |
Download PDF: