MEMORY/LOGIC CONJUGATE SYSTEM

WIPO Patent Application WO/2010/001833

A1

There is a problem in that when an increase in scale is dealt with using a crossbar switch, a bandwidth bottle neck occurs.  Provided is a memory/logic conjugate system wherein a plurality of cluster memory chips, each including a plurality of cluster memories (20) in which basic cells (10) that have a memory circuit are disposed in the form of a cluster, and a controller chip for controlling the plurality of cluster memories are stacked in a three dimensional manner.  The plurality of cluster memories (20) arranged in the stacking direction of the plurality of cluster memory chips and the controller chip, are electrically connected to the controller chip via a multibus (11) including a through-hole via, and an arbitrary basic cell (10) is switched to a logic circuit by directly accessing the arbitrary basic cell (10) from the controller chip via the multibus (11), and writing truth value data.

OTSUKA KANJI (JP)
ITO TSUNEO (JP)
SATO YOICHI (JP)
YOSHIDA MASAHIRO (JP)
YAMAMOTO SHIGERU (JP)
KOYAMA TAKESHI (JP)
TANBA YUKO (JP)
AKIYAMA YUTAKA (JP)

PCT/JP2009/061741

January 07, 2010

June 26, 2009

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TAMA TLO LTD (JP)
MEISEI GAKUEN (JP)
OTSUKA KANJI (JP)
ITO TSUNEO (JP)
SATO YOICHI (JP)
YOSHIDA MASAHIRO (JP)
YAMAMOTO SHIGERU (JP)
KOYAMA TAKESHI (JP)
TANBA YUKO (JP)
AKIYAMA YUTAKA (JP)

G06F7/00; H03K19/177

WO2007060738A1

2007-05-31

JP2008078596A	2008-04-03
JP2007165589A	2007-06-28

KANJI OTSUKA: "Looking at the Turning Point of Packaging Technology for Communication Systems", JOURNAL OF JAPAN INSTITUTE OF ELECTRONICS PACKAGING, vol. 10, no. 5, 1 August 2007 (2007-08-01), RENSHI SAWADA, pages 344 - 348

YANASE, Mutsuyasu et al. (JP)
Mutsuyasu Yanase (JP)

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