Title:
A/D CONVERSION CIRCUIT AND SOLID-STATE IMAGE PICKUP APPARATUS
Document Type and Number:
WIPO Patent Application WO/2015/159454
Kind Code:
A1
Abstract:
An A/D conversion circuit comprises: a ramp signal generation unit; a phase signal generation unit that outputs a phase clock; a comparison unit that outputs a comparison result signal the voltage of which varies at a constant rate from a time when a result of comparison between a signal voltage to be converted and a ramp signal voltage satisfies a predetermined condition; a signal generation unit comprising both a first logic circuit that switches the logic status of a first timing signal at a first timing when the voltage of the comparison result signal becomes equal to or greater than a first voltage and a second logic circuit that switches the logic status of a second timing signal at a second timing when the voltage of the comparison result signal becomes equal to or greater than a second voltage; a latch unit comprising a latch circuit that latches the logic status of the phase clock in response to at least one of the first and second timings, said latch unit outputting the logic status of the phase clock as phase information; and an encode unit that generates, on the basis of the phase information, a digital value in accordance with the magnitude of the voltage of the signal to be converted.
More Like This:
Inventors:
KOYAMA YUSAKU (JP)
Application Number:
PCT/JP2014/081109
Publication Date:
October 22, 2015
Filing Date:
November 25, 2014
Export Citation:
Assignee:
OLYMPUS CORP (JP)
International Classes:
H03M1/56; H04N5/378
Foreign References:
| JP2014045432A | 2014-03-13 | |||
| JP2011254246A | 2011-12-15 | |||
| JPH05191261A | 1993-07-30 | |||
| JPS6324655A | 1988-02-02 |
Attorney, Agent or Firm:
TANAI Sumio et al. (JP)
Sumio Tanai (JP)
Sumio Tanai (JP)
Download PDF: