[ 0001 ] A delay-locked loop ( DLL ) circuit is a digital controlled loop that allows generating a clock with a defined delay or phase shift with respect to a reference clock . The delay or phase shift is usually generated using a variable delay line . That is , the DLL can be considered as a feedback circuit that phase locks an output to an input without the use of an oscillator . It can be used, for example , to control a delay or phase shift of signals in a ranging sensor such as a time-of-f light (TOF ) sensor or a Light Detection and Ranging (LiDAR) sensor .

[ 0002 ] While traversing a corresponding chip of such a sensor said signals have different propagation delays depending on their respective sources as well as process , voltage- , and temperature- induced fluctuations . This unknown delay of a signal path results in signal distortions that affect the performance of the sensor .

[ 0003 ] Concepts are therefore being sought , by which a DLL circuit enables effectively equalizing delays of signals with high performance .

[ 0004 ] It is therefore an obj ect of the present invention to provide an improved delay-locked loop circuit . The above obj ect is achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

SUMMARY

[ 0005 ] According to embodiments , a delay-locked loop ( DLL ) circuit for generating a signal that has a defined delay or phase shift comprises : a pulse generator configured to generate a pulse signal that is input to a circuit having an unknown delay, a variable delay line configured to receive the pulse signal after traversing through the circuit with the unknown delay and to generate an output signal , and a comparator configured to receive the output signal and to compare the output signal with a reference signal , the reference signal having a fixed delay or phase shift , The DLL circuit is further configured to adapt a delay of the variable delay line depending on the result of the comparison .

[ 0006 ] Using this circuit it is possible to measure the unknown delay or phase shift caused by the circuit with unknown delay . Furthermore , it is possible to equalize the delay such that all signals passing through the circuit with unknown delay have a fixed delay or phase shift . This fixed delay or phase shift corresponds to the delay or phase shift of the reference signal . For example , the DLL can be applied in a laser driver to equalize delays within an analog chain of said driver .

[ 0007 ] In this context , the reference signal may be generated by a reference delay line .

[ 0008 ] The fixed delay or phase shift of the reference signal may be compared with a delay or phase shift of the output signal .

[ 0009 ] The output signal may have a delay or phase shift set by the variable delay line in addition to an external delay or phase shift due to traversing the external circuit having the unknown delay .

[ 0010 ] The pulse generator may generate a further pulse signal that is input into the circuit having the unknown delay after the delay of the variable delay line has been adapted .

[ 0011 ] Applying further pulsed signals may allow adj usting the delay of the variable delay line until the output signal has a delay or phase shift that corresponds to the reference signal . In other words , it may be possible to calibrate the variable delay line such that the output signal has the delay or phase shift corresponding to that of the reference signal .

[ 0012 ] The DLL circuit may further generate a LOCK signal when the delay or phase shift of the output signal corresponds to the fixed delay or phase shift of the reference signal . The LOCK signal can have the same delay or phase shift as the reference signal .

[ 0013 ] The DLL circuit may further comprise a logical circuit that is configured to control the pulse generator , the variable delay line , and the comparator .

[ 0014 ] For example , the logical circuit may provide a signal to the pulse generator to generate a pulse signal . It may be further able to control the variable delay line such that a delay is added or subtracted .

[ 0015 ] The comparator may generate an up-signal when the delay or phase shift of the output signal is smaller than the fixed delay or phase shift of the reference signal . It may generate a down-signal when the delay or phase shift of the output signal is larger than the fixed delay or phase shift of the reference signal . It can send the up-signal or the down-signal to the control circuit .

[ 0016 ] The comparator may for example compare the rising edges of the reference signal to the output signal .

[ 0017 ] The control circuit may further generate a control signal to add a delay on the variable delay line when receiving the up-signal . It can generate a control signal to subtract a delay on the variable delay line when receiving the down-signal . It may then send the control signal to the variable delay line .

[ 0018 ] In addition, the control circuit may further sum the up- and down-signals from the comparator . From this it is possible to derive the external delay or phase shift due to the circuit having the unknown delay .

[ 0019 ] The delay of the variable delay line may be increased or decreased according to the control signal by adding or subtracting delay units of the variable delay line . The delay units may each have a fixed delay . [ 0020 ] According to embodiments , a method for generating a signal that has a defined delay or phase shift may comprise the following steps : generating a pulse signal that is input into a circuit having an unknown delay, receiving the pulse signal after traversing the circuit having the unknown delay and generating an output signal , comparing the output signal to a reference signal , the reference signal having a fixed delay or phase shift , and adapting a delay of a variable delay line depending on the result of the comparison .

[ 0021 ] In addition, the method may include comparing the fixed delay or phase shift of the reference signal to a delay or phase shift of the output signal .

[ 0022 ] Furthermore , the method may include generating a further pulse signal that is input into the circuit having the unknown delay after the delay of the variable delay line has been adapted .

[ 0023 ] Moreover, the method may include generating a LOCK signal when the delay or phase shift of the output signal corresponds to the fixed delay or phase shift of the reference signal , the LOCK signal having the same delay or phase shift as the reference signal .

[ 0024 ] According to embodiments , an integrated circuit comprises the DLL circuit as described above .

[ 0025 ] According to embodiments , an electrical device comprises the DLL circuit as described above .

[ 0026 ] The electrical device may be selected from a Light Detection and Ranging (LiDAR) system, a time-of-f light ( TOF) sensor, a biomedical application or an electronic device for use in automotive applications .

BRIEF DESCRIPTION OF THE DRAWINGS

[ 0027 ] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification . The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles . Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description . The elements of the drawings are not necessarily to scale relative to each other . Like reference numbers designate corresponding similar parts .

Fig . 1 is a schematic diagram illustrating a delay-locked loop circuit according to embodiments . The delay-locked loop circuit according to embodiments may be used in combination with an external circuit or circuits .

Fig . 2A shows signals generated by components of the delay-locked loop circuit according to embodiments .

Fig . 2B shows signals generated by components of the delay-locked loop circuit according to embodiments .

Fig . 3 illustrates components of a variable delay line according to embodiments .

Fig . 4 is a schematic diagram illustrating a method according to embodiments .

Fig . 5A shows a schematic view of an integrated circuit according to embodiments .

Fig . 5B shows a schematic view of an electronic device according to embodiments .

DETAILED DESCRIPTION

[ 0028 ] In the following detailed description reference is made to the accompanying drawings , which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims.

[0029] The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments .

[0030] As employed in this specification, the terms "coupled" and/or "electrically coupled" are not meant to mean that the elements must be directly coupled together - intervening elements may be provided between the "coupled" or "electrically coupled" elements. The term "electrically connected" intends to describe a low-ohmic electric connection between the elements electrically connected together.

[0031] As used herein, the terms "having", "containing", "including", "comprising" and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0032] Fig. 1 is a schematic diagram illustrating a delay-locked loop (DLL) circuit 10 according to embodiments. The DLL circuit 10 comprises a pulse generator 12, a variable delay line 16, a comparator 18, and a logical circuit 20. In addition, a circuit 14 having an unknown delay is shown as an external component. For example, external circuits such as the illustrated circuit 14 may be circuits that are not contained in the DLL circuit 10. [0033] The pulse generator 12 generates a pulse signal S _pu ise that is input to the circuit 14 having an unknown delay. This is shown by an arrow in Fig. 1.

[0034] The variable delay line 16 receives the pulse signal S _pu ise after the pulse signal S _pu ise has traversed or passed through the circuit 14 with the unknown delay. This signal, indicated in Fig. 1 by Stest, serves as a test signal used to calibrate the variable delay line 14 as explained in detail later on. The variable delay line 16 then generates an output signal S _ou t depending on the test signal Stest, i.e. the pulse Signal S _pu ise having an unknown external delay or phase shift t _ex t due to traversing the circuit 14.

[0035] In this regard, Fig. 2A shows signals generated by components of the DLL circuit 10 according to embodiments. For example, the pulse signal S _pu ise may comprise a first pulse having a length of t _P uise (e.g., 3.336 ns (generated with a 1/ti clock, not shown in Fig. 1) , followed by another pulse after a certain period of time, which is, for example, about 53 ns. When crossing the circuit 14 having the unknown delay, the pulse signal S _pu ise obtains the external delay text or phase shift resulting in the test signal Stest - This external delay t _ex t or phase shift is illustrated in Fig. 2A. Furthermore, the output signal S _ou t has, in addition to the external delay text, the delay added by the variable delay line 16.

[0036] The comparator 18 receives the output signal S _ou t and compares the output signal S _ou t with a reference signal S _r et- The reference signal S _re t has a fixed delay or phase shift. In the example of Fig. 2A, the reference signal S _re t may have a pulse with a length similar to the pulse of the pulse signal S _pu ise •

[0037] The DLL circuit 10 further adapts a delay of the variable delay line 16 depending on the result of the comparison.

[0038] For example, as explained in detail in the following, a delay of the variable delay line 16 is adapted such that a delay or phase shift of the output signal S _ou t is similar to the delay or phase shift of the reference signal S _re f- In other words, the variable delay line 16 is used to generate a signal that has the fixed delay or phase shift of the reference signal S _re f- Thus, different from applications, where a DLL circuit is used to calibrate a delay or phase shift of a clock, the DLL circuit 10 according to the present invention allows calibrating the variable delay line 14 to generate a signal that has the fixed delay or phase shift of the reference signal S _re f-

[0039] The calibrated variable delay line 16 enables equalizing the external delay t _ex t or phase shift (i.e. , a variable unknown delay or phase shift of a signal path within the circuit 14) by adapting the delay or phase shift of the variable delay line 16 such that the sum of both delays or phase shifts corresponds to the fixed delay or phase shift of the reference signal S _re f-

[0040] In other words, it is possible to account for a propagation delay or phase shift of signals traversing the circuit 14 (e.g. , provided on a chip of a ranging sensor) in a manner that all signals have the same delay or phase shift. That is, it is possible to calibrate the propagation delay in a chip for all signals to a fixed delay or phase shift.

[0041] Furthermore, with this approach it is possible to measure the variable unknown delay of the signal path within the circuit 14, which will be explained in relation to Fig. 3.

[0042] The reference signal S _re f may thereby be generated by a reference delay line (not shown in Fig. 1) . It is sent to the comparator 18 by the pulse generator 12 as shown by a corresponding arrow in Fig. 1.

[0043] Turning to the comparison, the fixed delay or phase shift of the reference signal S _re f may be compared with the delay or phase shift of the output signal S _ou t- [ 0044 ] As discussed above , the output signal S _ou t may have a delay or phase shift set by the variable delay line 16 in addition to the external delay t _ex t or phase shift due to traversing the external circuit 14 having the unknown delay .

[ 0045 ] For example , if the resulting difference between the output signal S _ou t and the reference signal S _re f is negative , then the delay or phase shift of the variable delay line 16 was smaller than the fixed delay or phase shift of the reference signal S _re f - The delay of the variable delay line 16 is then to be increased . On the other hand, if the resulting difference is positive , then the delay of the variable delay line 16 was too large and the delay of the variable delay line is to be decreased . This is explained in greater detail with reference to Fig . 3 later on .

[ 0046 ] The pulse generator 12 can generate a further pulse signal Spuise that is input into the circuit 14 having the unknown delay after the delay of the variable delay line 16 has been adapted . For example , additional pulses of the pulsed signal can enter the circuit 14 and then be used as test signals Stest to calibrate the variable delay line 16 as discussed above . The pulsed signals S _pu ise are sent many times in order adapt the delay of the variable delay line 16 such that the fixed delay or phase shift is reached .

[ 0047 ] The DLL circuit 10 can generate a LOCK signal Si _OC k when the delay or phase shift of the output signal S _ou t corresponds to the fixed delay or phase shift of the reference signal S _re f - The LOCK signal Si _OC k can have the same delay or phase shift as the reference signal S _re f - The lock signal Si _OC k will exit from the comparator 18 that generates also the up and down signals .

[ 0048 ] For example , Fig . 2B shows signals generated by components of the DLL circuit 10 according to embodiments including the LOCK signal Si _OC k, the output signal S _ou t, and the reference signal S _re f - As can be seen, the LOCK signal Si _OC k is generated when the delay or phase shift of the output signal S _ou t and the reference signal S _re f coincide . [ 0049 ] Moreover , the logical circuit 20 as shown in Fig . 1 can control the pulse generator 12 , the variable delay line 16 , and the comparator 18 .

[ 0050 ] The comparator 18 can further generate an up-signal S _up when the delay or phase shift of the output signal S _ou t is smaller than the fixed delay or phase shift of the reference signal S _re f - It also may generate a down-signal Sdown when the delay or phase shift of the output signal S _ou t is larger than the fixed delay or phase shift of the reference signal S _re f - The up-signal S _up or the down-signal Sdown can be input into the control circuit 20 , as indicated by the respective arrows in Fig . 1 . For example , the comparator 18 may compare the rising edges of the reference signal S _re f and the output signal S _ou t -

[ 0051 ] The control circuit 20 can then generate a control signal Scontroi to add a delay on the variable delay line 16 when receiving the up-signal S _up . Furthermore , it can also generate a control signal Scontroi to subtract a delay on the variable delay line 16 when receiving the down-signal Sdown - The control circuit 20 can send the control signal Sdown to the variable delay line 16 as shown by an arrow in Fig . 1 .

[ 0052 ] The delay of the variable delay line 16 can then be increased or decreased according to the control signal S _con troi by adding or subtracting delay units 17 ( also known as buffers or taps ) of the variable delay line 16 . The delay units 17 may each have a fixed delay .

[ 0053 ] Fig . 3 illustrates components of a variable delay line according to embodiments . The logic circuit 20 uses the up-signal S _up or the down-siganl Sdown to generate the control signal S _con troi to select step by step one more or one less delay unit 17 of the variable delay line 16 , thereby increasing or decreasing the delay . That is , step by step the variable delay line 16 modifies its delay according to the control signal S _con troi that is generated depending on the up/down signal S _up , Sdown-

[0054] In one embodiment, the variable delay line 16 comprises 200 delay units 17 having a total delay of e.g., 20 ns (i.e., 100 ps per delay unit 17) . When starting the DLL circuit 10, a sequence of pulse signals S _pu ise is sent into the circuit 14 to be measured and equalized. With each pulse signal S _pu ise, the comparator 18 decides if to increase or decrease the delay of the variable delay line 16 to reach a value nearer the fixed delay or phase shift of the reference delay line. At the end of said procedure, i.e. after the pulse signals S _pu ise have been sent many times through the DLL circuit 10, the output signal S _ou t reaches the reference signal S _re f as shown in Fig. 2B. Then the calibration of the variable delay line 16 is finished and the LOCK signal Si _OC k is generated.

[0055] Thus, the unknown variable external delay t _ex t and the delay of the variable delay line 16 are equalized with the reference delay line, which can be used for other signals passing the circuit 14. In addition, the logic circuit 20 sums all the up/down pulses from the comparator 18, which allows obtaining a measured value of the delay. In general, the precision of this approach depends upon the frequency accuracy of a phase-locked loop (PLL) used to clock the logical circuit 20 and from the remaining propagation delay added by the comparator 18. Simulations indicate a final precision of about 100 ps that can be reached.

[0056] Fig. 4 illustrates a method for generating a signal that has a defined delay or phase shift according to embodiments. The method comprises the following steps .

[0057] In step S110, the pulse signal S _pu ise is generated that is input into the circuit 14 having an unknown delay.

[0058] In step S120, the pulse signal S _pu ise is received after traversing the circuit 14 having the unknown delay and an output signal (S _ou t) is generated. [0059] In step S130, the output signal S _ou t is compared to the reference signal S _re f- As described above, the reference signal S _re f has a fixed delay or phase shift.

[0060] In step S140, the delay of the variable delay line 16 is adapted depending on the result of the comparison.

[0061] In greater detail, in step S130, the fixed delay or phase shift of the reference signal S _re f can be compared to a delay or phase shift of the output signal S _ou t-

[0062] Furthermore, in step S110, a further pulse signal S _pu ise may be generated that is input into the circuit 14 having the unknown delay after the delay of the variable delay line 16 has been adapted. That is, after adapting the delay in the variable delay line 16 the procedure can start again with another pulse signal S _pu ise. This is indicated by the arrow in Fig. 4 that reverts back from step S140 to S110.

[0063] In step S150, the LOCK signal Si _OC k can be generated when the delay or phase shift of the output signal S _ou t corresponds to the fixed delay or phase shift of the reference signal S _re f- The LOCK signal Si _OC k can have the same delay or phase shift as the reference signal S _re f-

[0064] Fig. 5A shows an integrated circuit 1 comprising DLL circuit

10 as described above.

[0065] Fig. 5B shows an electrical device 5 comprising the DLL circuit 10 as described above.

[0066] The electrical device 5 can be selected from a LiDAR system, a TOF sensor, a biomedical application or an electronic device for use in automotive applications . [0067] For example, in a LiDAR system, the DLL circuit 10 may be used for equalizing delays of an analog chain for a LiDAR driver. As a result, the performance of the LiDAR system is improved.

LIST OF REFERENCES

1 integrated circuit

5 electronic device

10 delay-locked loop circuit

12 pulse generator

14 external circuit

16 variable delay line

17 delay unit

18 comparator

20 logic circuit

Spuise pulse signal

Sref reference signal

Sout output signal

S _U p up-signal

Sdown down-signal

S _C ontroi control signal

S iock lock signal

Stest test signal text external delay or phase shift tpuise length of pulse

S110 generating a pulse signal

S120 receiving the pulse signal and generating an output signal

S130 comparing the output signal

S140 adapting a delay

S150 generating a further pulse signal