DELAY SYNCHRONIZATION LOOP-BASED FORWARDED CLOCKING TYPE RECEIVER

WIPO Patent Application WO/2016/021840

A1

A delay synchronization loop according to the present invention includes a voltage control delay line and a phase detector, the phase detector (100) comprising: a sampler unit (120) for sampling a data signal on the basis of a clock, the sampler unit generating multiple samples having a time interval corresponding to a half of a unit interval; a mode selection unit (130) for selecting a series of samples among the multiple samples generated by the sampler unit (120), a mode selection unit (130) selecting a series of samples starting from an odd-numbered sample or selecting a series of samples starting from an even-numbered sample, according to a mode selection signal; and an XOR unit, in which the series of samples output from the mode selection unit (130) performs an XOR with adjacent samples, for outputting an outcome of the XOR, wherein the output of the XOR unit (140) is used for controlling the voltage control delay line. The present invention can greatly reduce power consumption and an area of the voltage control delay line which consumes a lot of electric power and occupies a chip area.

WO/2016/195898	DIGITAL DELAY-LOCKED LOOP (DLL) TRAINING
WO/2019/060143	LOW LATENCY ADAPTIVE CLOCKING
JP2011250236	PLL CIRCUIT AND DLL CIRCUIT

JEONG DEOGKYOON (KR)
BAE WOORHAM (KR)

PCT/KR2015/007049

February 11, 2016

July 08, 2015

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UNIV SEOUL NAT R & DB FOUND (KR)

H03L7/081; H03L7/085

WO2005122460A1

2005-12-22

US20070058768A1	2007-03-15
US6166572A	2000-12-26
US20080273430A1	2008-11-06
US20030118209A1	2003-06-26

TAESAN PATENT & LAW FIRM (KR)
특허법인태산 (KR)

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