Digital controlled oscillator

The present invention generally relates to an electronic device with a digital controlled oscillator (DCO).

Fully integrated RC oscillators are limited in performance compared to oscillators that use a high Q resonator, as for example crystal oscillators. Initial frequency accuracy, frequency drift over temperature and voltage and phase noise are always worse in fully integrated oscillators than in an oscillator comprising a high Q resonator. However, it is desirable to use RC oscillators instead of crystal oscillators, as they can be fully integrated in a CMOS technology, which reduces complexity and production costs.

It is an object of the present invention to provide an electronic device including a digital oscillator with an improved accuracy and long term stability of the oscillation frequency.

Accordingly, the present invention provides an electronic device comprising a digital controlled oscillator. The digital controlled oscillator includes a programmable current source, a first variable capacitor, and a second variable capacitor. A comparator is provided for comparing the voltage drop across the variable capacitors with a reference voltage level, and for providing a DCO output clock signal. A switching means alternately switches the variable capacitors to receive either a current from the programmable current source or to be discharged in response to an output signal of the comparator. Further, a clock divider is coupled to the comparator output for dividing the DCO output clock signal by a factor N, which is substantially greater than 1 , in order to provide a divided clock signal. Further, a frequency monitoring stage is provided for receiving the divided clock signal. The frequency monitoring stage is adapted to determine the time difference of successive clock periods of the divided clock signal and to generate a feedback signal based on the determined time difference. The DCO is coupled to the feedback signal for adjusting the DCO output clock frequency in response to the feedback signal. An advantageous way of adapting the DCO frequency consists in adapting the capacitance values of the variable capacitors with the feedback signal. Preferably, the factor N is chosen such that a period of the divided clock signal is in proportion to a temperature, supply voltage or other degradation induced deviation of the DCO output clock signal. Advantageously, the monitoring stage is adapted to compare pairs of consecutive divided clock periods, such that each divided clock period is compared with a preceding divided clock period and with a following divided clock period. This ensures continuous, consistent and reliable control.

In a conventional DCO architecture, component properties, as for example resistances, capacitance values, delay times as well as comparator offset voltages etc. are temperature and supply voltage dependent. Even with a high-precision reference voltage or current generator (e.g. bandgap reference voltage source) the achievable overall accuracy of the oscillator will be in a range of only 2% to 5%. The initial oscillator frequency can be trimmed easily by various means. For example, the reference current or the capacitors can be changed by a trimming scheme. However, to get the overall accuracy of the oscillator in the range of a crystal oscillator (e.g. 20 to 50 ppm), further improvements are required. Accordingly, the present invention suggest to choose the factor N in accordance with a temperature deviation, and/or a supply voltage induced deviation or any similar slow deviation that is to be compensated. As long as the deviation is relatively slow compared with the oscillating frequency, the present invention provides a convenient, easy and effective means, so that the oscillator output frequency is scaled to the frequency deviation. It is therefore a special aspect of the invention to scale down a DCO output frequency in a range where a clock frequency of a downscaled clock signal can be used as an indicator for a frequency deviation, which is much slower than the DCO clock frequency. The way to determine the frequency deviation is differential and self-regulating, which means that successive clock periods of the downscaled clock are compared with each other and the comparison result is used to adjust the DCO frequency.

Preferably, the frequency monitoring stage comprises an adjustable current source, three calibration capacitors, a comparator, switching means to alternately couple one of the three calibration capacitors to the adjustable current source, and two of the three calibration capacitors to the second comparator, in order to compare the voltage levels on the calibration capacitors. A controlling means is provided for controlling the switching means such that either one of the calibration capacitors is successfully charged with the current from the adjustable current source over a period of the divided clock signal to a respective maximum voltage level. Two maximum voltage levels are then consecutively selected and compared by the comparator in each clock period of the divided clock. A reference signal is generated by a voltage ramp. This voltage ramp is sampled by the oscillator output signal. The difference in amplitude of two successive samples is a measure of the frequency drift or change and is used as an input for a digital control block implemented by the controlling means. The output of the control block then controls the three calibration capacitors. To optimize the tuning process, the digital control block can use an algorithm (e.g. a search algorithm), for example a binary weighting scheme. In this way, both coarse and fine tuning of the feedback loop can be efficiently, achieved.

Preferably, the device further comprises a weighting stage coupled between the output of the second comparator and the variable capacitors of the digital controlled oscillator for

weighting the output signal of the second comparator. This weighting stage can include a counter, which is increased and decreased in response to the comparator output. The counter can be an up-and-down counter, such that if the voltage difference is positive, the counter value is increased by 1 , but if the voltage difference is negative, the counter value will be decreased by 1. The output of the counter or an average value thereof then controls the capacitive array by adjusting the capacitance of the first and second capacitors up or down so as to compensate for frequency drift of the output signal of the DCO. Although it is preferred to adjust the capacitance of the DCO, other ways to adjust the DCO frequency are generally conceivable, like e.g. adjusting a current in the DCO or a resistor.

Preferably, each of the variable capacitors comprises two portions. In the first portion, the capacitance is adjusted in response to the feedback signal, and in the second portion there is a constant capacitance value. This means that the fine tuning of the DCO output clock signal can be achieved by varying the capacitance of the variable capacitors around their constant value.

The present invention also provides a method for adjusting the oscillation frequency of a digital controlled oscillator. The method comprises dividing the frequency of the output clock signal of the DCO, comparing the length of successive periods of the divided clock signal, and adjusting the output clock frequency of the DCO in response to the comparison result. The frequency drift of the DCO is mainly caused by limited power supply rejection (PSRR) of the oscillator and temperature/voltage drift of component parameters. Therefore, the present invention suggest to establish a self-control mechanism, wherein the instantaneous frequency of the DCO oscillating frequency is determined in successive points in time. The difference of these measurement results (i.e. the difference of the length or duration of the different periods) is directly proportional to the frequency change and is advantageously used in a control loop to reduce the error. Advantageously, a variable capacitor in the DCO can be adjusted for tuning the frequency. Further, always pairs of consecutive clock periods of the divided clock signal can be compared, and firstly, a first clock period of the divided clock signal is compared with a second clock period and next the second clock period is compared with a third clock period. Accordingly, each clock period of the divided clock signal is compared with a predecessor and a successor before it is dismissed from being monitored, which provides a continuous and reliable control. The method of the present invention provides the advantage that the scheme is not using an amplitude control loop or phase locked loop scheme, where the oscillating frequency is compared with a reference signal. Instead, the circuit is using a mainly digital tuning and trimming scheme in a feedback configuration, thereby establishing a self-controlling DCO. It allows a very simple and area-efficient implementation of a fast acquisition scheme, due to the mainly digital realization of the circuitry. No complex low-frequency analogue filters are required

for the control loop. Furthermore, the present invention provides the advantages of a reliable operation. An area-efficient implementation is also provided, which has a wide operating frequency range (e.g. 100 kHz - 40 MHz). Additionally, the adjustable current source providing current for the three capacitors can be implemented so as to be adjustable on the basis of the resistance of a single resistor. If such a resistor is implemented externally, i.e. not integrated with the other components on the same die, the high accuracy of the device depends only on an external resistor and can be easily adjusted.

Further characteristics and advantages of the invention ensue from the description below of a preferred embodiment, with reference to the accompanying drawings, in which:

- Figure 1 is a simplified circuit diagram of a digital controlled oscillator for use in the device according to a first embodiment of the invention;

- Figure 2 is a simplified circuit diagram of a device according to a second embodiment of the invention;

- Figure 3 is a schematic diagram of frequency and voltage against time for the device of the present invention under stable conditions; and

- Figure 4 is a schematic diagram of frequency and voltage against time for a device according to the present invention under unstable conditions, for example due to temperature drift.

Figure 1 shows a digital controlled oscillator (DCO) as part of the device according to the invention. A programmable current source Ipr, which is implemented as a MOS transistor, is connected between a supply voltage rail Vdd and a voltage rail V _AB , and is adapted to provide a reference current I ₀ . The gate terminal of the MOS transistor implementing the current source Ipr is operable to receive a control voltage V _CNTL - The voltage rail V _AB forms one input of a comparator COMP. The other input of the comparator COMP is provided by a reference voltage Vref. The output of the comparator COMP is connected to an inverter INV1 , which is connected in series with another inverter INV2. The output of the inverter INV2 is connected to a divide by N clock divider %N and the clock divider %N is coupled to a frequency monitoring stage FMS. The frequency monitoring stage FMS is connected to a bus L1. The inverter INV1 is configured to output a first control signal A and the inverter INV2 is configured to output a second control signal B, which is the inverse of the control signal A.

Two capacitors C _A and C ₆ are connected in parallel with each other between the voltage rail V _AB and ground, via respective switches S1A and S1 B. Both capacitors C _A and C ₆ are also connected to the bus L1 , the signal from which is operable to vary the capacitance of the

capacitors C _A and C _B . The capacitor C _A is also connected in parallel with a switch S2B and the capacitor C ₆ is connected in parallel with a switch S2A, such that the switches S2A and S2B are both connected to ground. The switch S2A is also connected to a node interconnecting the switch S1 B and the capacitor C ₆ and the switch S2B is connected to a node interconnecting the switch S1A and the capacitor C _A . The switches S1A and S2A are operable to be controlled by the signal A output from the inverter INV1 and the switches S1 B and S2B are operable to be controlled by the signal B output from the inverter INV2. The switches can be implemented, for example, by MOS transistors.

In operation, the comparator COMP compares the voltage drop across the variable capacitors C _A and C ₆ at the voltage rail V _AB with the reference voltage Vref. The output of the comparator COMP is then the DCO output clock signal, which is generated based on the difference between the voltage V _AB and the reference voltage Vref. If the voltage at the voltage rail V _AB is greater than the reference voltage Vref, the output of the comparator COMP will be positive, which means that the output signal A output from the inverter INV1 is negative and the output signal B output from the inverter INV2 is positive. This means that the switches S1A and S2A are opened and the switches S1 B and S2B are closed, such that the capacitor C _A discharges to ground via the closed switch S2B and the capacitor C _B is charged by the reference current I ₀ . When the voltage at the voltage rail V _AB becomes less than the reference voltage Vref, the output of the comparator is negative and the opposite of the above occurs, so that the output signal A is positive and the signal B is negative. Switches S1A and S2A are closed and switches S1 B and S2B are opened so that the capacitor C _B discharges to ground via the closed switch S2A and the capacitor C _A is charged by the reference current I ₀ . Thus the capacitors C _A and C _B are alternately switched to receive either a current I ₀ from the programmable current source lpr or to be discharged and the DCO periodically toggles between charging and discharging of the capacitors C _A and C _B , which generates the output frequency of the DCO.

Ideally, the output frequency of the DCO should look like the uppermost diagram in Figure 3, which shows the divided output frequency X (as divided by the clock divider %N at the output of the comparator COMP) against time under stable conditions. In other words, the output of the DCO should be a regular periodic output signal with no frequency drift. However, any temperature changes can cause the frequency to drift so that the time period between successive output signals becomes longer and longer and the divided output frequency X against time looks like that shown in the top graph in Figure 4. The required time period between output signals is t ₀ , which is the time gap between the first two signals. By the time the third signal is output, the time period between the second and third output signals has increased

to to + δt, then between the third and fourth output signals to t ₀ + 2δt, and so on, increasing by an amount δt after every consecutive output signal. To prevent this frequency drift, the clock divider %N is configured such that the factor N divides the output of the comparator COMP; i.e., the output frequency of the DCO, so that the period of the divided clock signal is chosen so as to compensate a temperature or supply voltage induced deviation of the DCO output clock signal. Generally, the control loop established through divider %N, the frequency monitoring stage FMS and the adjustable capacitors has a characteristic (delay, settling time, frequency response etc.), which provides a stable feedback control, but in proportion to a specific frequency deviation relating to a temperature or supply voltage. The frequency monitoring stage FMS then receives the divided clock signal X and determines the time difference of successive clock periods of the divided clock signal X. Based on the determined time difference, the frequency monitoring stage generates a feedback signal in response to the determined time difference. The feedback signal then adjusts the capacitance values of the variable capacitors CA and CB either up or down to compensate for the time difference, which corrects the frequency drift of the signal output from the DCO.

Figure 2 shows a specific implementation of the frequency monitoring stage FMS. The components of the DCO are identical to those shown in Figure 1 and will not be described further. In this embodiment, the clock divider %N is implemented as two clock dividers /M and /N connected in series, with the first clock divider /M being directly connected to the output of the second inverter INV2. The divided frequency X is then output from the second clock divider /N and fed to the input of a state machine SM. The state machine SM has several outputs. Two of the outputs are connected to control inputs of the clock dividers /M and /N, and are operable to provide control signals N1 and N2 to the control inputs of the clock dividers /M and /N, respectively. A further three outputs are connected to three switches S1 , S2 and S3 and are operable to output control signals CS1 , CS2 and CS3 to the three switches S1 , S2 and S3, respectively, for controlling switching of the switches S1 , S2 and S3. The switches S1 , S2 and S3 are connected in parallel with each other between an adjustable current source ladj and three capacitors C1 , C2 and C3, respectively, so that the capacitors C1 , C2 and C3 are respectively switched by the switches S1 , S2 and S3. The adjustable current source ladj is also connected to the supply voltage rail Vdd. The adjustable current source can be implemented by a single resistor, which can preferably implemented externally to an integrated circuit incorporating the other components. Such an external resistor can be adjusted easily for calibration purposes. Three nodes interconnecting the switches S1 , S2 and S3 with the capacitors C1 , C2 and C3, respectively, are each connected to a switch matrix. The nodes 111 , U2 and U3 represent the voltage across the capacitors C1 , C2 and C3, respectively. The switch matrix has two outputs Up and Un, with Up being connected to the positive input of a second

comparator COMP2 and Un being connected to the negative input of the second comparator COMP1. The output of the second comparator COMP2 is connected to a weighting logic stage W and is adapted to output a signal Ucomp. The output of the weighting logic stage W is connected via the bus to the control inputs of the variable capacitors CA and CB in the DCO.

The six graphs of the voltages U1 , U2, U3, Up, Un and Ucomp in the frequency monitoring stage against time, below the graph of divided output frequency X, in Figures 3 and 4 show how the frequency monitoring stage of the second embodiment works. Figure 3 shows the DCO under stable conditions and Figure 4 shows the DCO when there is a drift in the output frequency due to, for example, temperature changes. The three calibration capacitors C1 , C2 and C3 are successively charged using a reference current lref provided by the adjustable current source ladj, which is ramped up over a period of the divided clock signal to a respective maximum voltage level so that the nodes U1 , U2 or U3 are at the maximum voltage level of the respective capacitor C1 , C2 or C3. In Figures 3 and 4, the voltage at the node U1 is ramped up to its maximum voltage level over the first clock period of the divided output signal X, by closing the switch S1 using the control signal CS1 from the state machine SM and leaving switches S2 and S3 open so that the capacitor C1 is charged with the reference current lref, so that the maximum voltage level at the node U1 is reached and maintained for the duration of the output clock signal. For the second clock period of the output clock signal X, the voltage at the node U2 is ramped up to a maximum level following the same procedure as above, by closing the switch S2 using the control signal CS2 so as to charge the capacitor C2 with the reference current lref. During the third clock period, the voltage at the node U3 is ramped up to a maximum level, by closing the switch S3 with the control signal CS3 and charging the capacitor C3. This process is repeated continuously so that the voltage at the nodes U1 , U2 and U3 is consecutively ramped up in a continuous loop.

The switch matrix MAT then consecutively selects two of the maximum voltage levels at U1 , U2 or U3, designated Up and Un when they are output from the switch matrix MAT, which are input to the positive and negative inputs of the second comparator C0MP2, respectively. From Figures 3 and 4 it can be seen that, after the first period of the divided output clock signal X, the voltage at U3, taken from the previous clock period, is compared with the voltage U1 , from the current clock period, so that Up = U3 and Un = UL The comparator C0MP2 compares the two maximum voltage levels Up and Un from the current and previous output clock periods and outputs a signal Ucomp representative of the difference between the two voltage levels Up and Un. The signal Ucomp output from the comparator C0MP2 is then input to the weighting logic stage W. A counter can be provided in the weighting logic stage W, which is then either increased or decreased in response to the output of the comparator C0MP2. The capacitance

of the capacitors CA and CB are varied up or down in response to the counter output, so that the output signal of the DCO is maintained at a constant frequency. Additional weighting steps may be applied to the counter value for improved performance. In Figure 3, when the DCO is operating under ideal, stable conditions, the frequency of the divided DCO output signal X is constant, therefore the voltages Up and Un are always equal and opposite to each other and cancel each other out when compared by the comparator C0MP2. The output of the comparator C0MP2 is then always zero, the counter in the weighting logic stage W does not count up and down and the capacitance of the capacitors CA and CB in the DCO remains constant. However, as shown in Figure 4, when the DCO is operating under unstable temperature conditions, as the output frequency drifts, so that the time period between output signals increases, the control signals CS1 , CS2 and CS3 output from the state machine SM cause the switches S1 , S2 and S3 to respectively remain closed for progressively longer periods of time. The ramps of U1 , U2, and U3 still have the same slope, but they increase for a longer time. The increase exceeding the ideal maximum voltage is indicate with a filled area on top of each of the voltages. This means that the maximum voltage at the nodes U1 , U2 and U3 gets larger for each consecutive clock period. For the example shown in Figure 4, the difference between the voltages Up and Un at the output of the comparator is -1 for each consecutive clock period. In response to the comparator result, the counter in the weighting logic stage may then count down by 1 unit each clock period, decreasing the capacitance of the capacitors CA and CB, and thereby correcting the frequency drift of the output signal of the DCO.

The circuit according to the present invention establishes a self-regulating DCO, the characteristics of which can be adapted to any specific system requirements. The parameters of the circuitry, as for example the clock dividers, the capacitance of the capacitors, the magnitude of the currents, can be easily determined by empirical studies or simulations.

Although the present invention has been described with reference to specific embodiments, it is not limited to these embodiments and no doubt further alternatives will occur to the skilled person that lie within the scope of the invention as claimed.