DIGITAL EDGE SUPER GENERATOR

WIPO Patent Application WO/1987/002209

A1

A circuit (31) for calculating a vertical edge width has a plurality of delay circuits (31a to 31h) connected in series, each of which having a delay time within a horizontal period. A circuit for calculating a horizontal edge width has a plurality of single-picture element delay circuits (32a to 32h) corresponding to the above edge widths to obtain horizontal distances between an input digital super key signal and raster positions. The minimum value of the plurality of euclidean distances between the digital super key signal and the raster positions obtained from ROMs (33a to 33s) from the vertical and horizontal distances obtained by these circuits is output as the actual euclidean distance from a detector (34).

JP3091960	Description: A machine-readable recording medium on which a pseudo-three-dimensional image display device, a pseudo-three-dimensional image display method, and a computer program are recorded.
WO/2019/070679	METHOD AND DEVICE FOR HOLE FILLING OF A POINT CLOUD
JP3054301	[Title of Invention] Image processing method and apparatus

SHINOHARA NOBUTAKA (JP)
HIRAKAWA SHUJI (JP)
MINAMI AKIHIKO (JP)
TANAKA KOICHI (JP)

PCT/JP1983/000204

April 09, 1987

June 24, 1983

Click for automatic bibliography generation  

SHINOHARA NOBUTAKA (JP)
HIRAKAWA SHUJI (JP)
MINAMI AKIHIKO (JP)
TANAKA KOICHI (JP)

G06T17/00; H04N5/278; G09G5/36; G09G5/377; H04N5/262; H04N5/445; (IPC1-7): H04N5/22

JPS5248668Y2	1977-11-05
JPS5242330B2	1977-10-24
JPS5321812B2	1978-07-05
JPS49111543A	1974-10-24
JPS4421763Y1	1969-09-16

View/Download PDF      PDF Help

Previous Patent: NETWORK IMPLEMENTED PAY TELEPHONE SET

Next Patent: PROCESS FOR CORRECTING TRANSMISSION ERRORS