Title:
DML DRIVER
Document Type and Number:
WIPO Patent Application WO/2021/205533
Kind Code:
A1
Abstract:
A predriver (3) is formed from: a transistor (M1n) in which a signal (Ｖin) is input into a gate; a load resistor (R1); a peaking inductor (L1); a peaking inductor (L2); a transistor (Ｍ1p) in which a control voltage (Vcon_p) is input into a gate; a transistor (Ｍxn) in which a control voltage (Vcon_n) is input into a gate; a group delay suppression inductor(Lx); a peaking capacitor(Cx); a peaking capacitor (Cy); and a peaking resistor (Rx).
Inventors:
KISHI TOSHIKI (JP)
NAGATANI MUNEHIKO (JP)
NOSAKA HIDEYUKI (JP)
NAGATANI MUNEHIKO (JP)
NOSAKA HIDEYUKI (JP)
Application Number:
PCT/JP2020/015638
Publication Date:
October 14, 2021
Filing Date:
April 07, 2020
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H04B10/50
Domestic Patent References:
| WO2018074410A1 | 2018-04-26 |
Foreign References:
| JP2013239641A | 2013-11-28 | |||
| JP2019165131A | 2019-09-26 | |||
| JP2009111168A | 2009-05-21 |
Other References:
MOTO A. ET AL.: "A Low Power Quad 25.78-Gbit/s 2.5 V Laser Diode Driver Using Shunt-Driving in 0.18 um SiGe-BiCMOS", 2013 IEEE COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM (CSICS), 2013, XP032525026
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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