IMPROVED ERROR CORRECTION SCHEME FOR USE IN FLASH MEMORY ALLOWING BIT ALTERABILITY

Title:

IMPROVED ERROR CORRECTION SCHEME FOR USE IN FLASH MEMORY ALLOWING BIT ALTERABILITY

Document Type and Number:

WIPO Patent Application WO2002086719

Kind Code:

A3

Abstract:

A system (70) comprising a microprocessor (74), a data bus (75) for writing data into a Flash memory device (71) and a data bus (75) for reading data from the Flash memory device (71). The Flash memory device (71) comprises an error correction encoder (72), a Flash memory (71), an error correction decoder (73), and a Flash data bus (75) for interconnecting the error correction encoder (72), the Flash memory (71), and the error correction decoder (73). The data, when being processed by the error correction encoder (72) are converted into a word that comprises a status word (51), a data word (52), and a redundancy word (53). This approach enables error correction with single-bit alterability.

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Inventors:

GAPPISCH STEFFEN
BAGGEN CONSTANT P M J
SLENTER ANDRE G J
GELKE HANS-JOACHIM

Application Number:

PCT/IB2002/001332

Publication Date:

January 15, 2004

Filing Date:

April 12, 2002

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Assignee:

KONINKL PHILIPS ELECTRONICS NV (NL)

International Classes:

G06F11/10; G06F11/08; G06F12/16; G11C16/06; G11C29/00; G11C29/42; (IPC1-7): G06F11/10

Foreign References:

US5448577A	1995-09-05
US6041001A	2000-03-21
US6151247A	2000-11-21

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