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Title:
INTEGRATED CIRCUIT DESIGN METHOD AND APPARATUS
Document Type and Number:
WIPO Patent Application WO/2023/279549
Kind Code:
A1
Abstract:
The present application discloses an integrated circuit design method and apparatus. A layout comprises: S1, loading a power fill on a circuit layout having original metal wiring; S2, checking whether the current layout comprises a region having a spacing error, if so, then entering S3, if not, then outputting the layout; and S3, cutting off a predetermined spacing width delta for a power fill pattern corresponding to each region having a spacing error, and returning to S2. The present application can help a layout engineer to efficiently solve a metal spacing error caused by adding a power fill on a layout, thereby saving time. A layout module that has been repaired by a tool can retain to the greatest extent an added power fill mesh while correcting the spacing error.

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WO/2013/108791SEMICONDUCTOR SEALING COMPOSITION, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME, AND POLYMER AND METHOD FOR PRODUCING SAME
Inventors:
CHEN CHUANJIANG (CN)
TANG LI (CN)
BAI LI (CN)
ZHAO KANG (CN)
Application Number:
PCT/CN2021/121362
Publication Date:
January 12, 2023
Filing Date:
September 28, 2021
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/768
Foreign References:
CN110390122A2019-10-29
CN101290904A2008-10-22
CN104932732A2015-09-23
US20060234166A12006-10-19
Attorney, Agent or Firm:
BEIJING LINKAW PATENT ATTORNEY LAW FIRM (CN)
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