Title:
INTER-DIE HIGH-SPEED EXPANSION SYSTEM AND METHOD
Document Type and Number:
WIPO Patent Application WO/2022/166426
Kind Code:
A1
Abstract:
An inter-die high-speed expansion system and method, for multi-protocol chip cascading and expansion. The inter-die high-speed expansion system comprises a cross-die expansion synchronizer and a direct pathway connected to the cross-die expansion synchronizer, the cross-die expansion synchronizer is disposed on a die, dies are connected by means of the cross-die expansion synchronizer and the direct pathway, the cross-die expansion synchronizer is used for controlling data transmission, and data comprises a clock signal, a reset signal, a handshake signal, and a data signal, wherein all the signals appear in pairs in a differential form. The system has good universality and low complexity, realizes flexible expansion of the interconnected dies, further constitutes a larger package-level network, and lays a foundation for subsequent microsystem integration.
Inventors:
WEI JINGHE (CN)
HUANG LETIAN (CN)
YU ZONGGUANG (CN)
ZHAO TIANJIN (CN)
JU HU (CN)
FENG MINGANG (CN)
HUANG LETIAN (CN)
YU ZONGGUANG (CN)
ZHAO TIANJIN (CN)
JU HU (CN)
FENG MINGANG (CN)
Application Number:
PCT/CN2021/138703
Publication Date:
August 11, 2022
Filing Date:
December 16, 2021
Export Citation:
Assignee:
58TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECH GROUP CORPORATION (CN)
International Classes:
G06F15/78
Foreign References:
| CN112817908A | 2021-05-18 | |||
| CN112817906A | 2021-05-18 | |||
| US20200104064A1 | 2020-04-02 | |||
| CN1570894A | 2005-01-26 |
Other References:
JIAN WANG,, LEI ZHANG, ZHEN WANG, ZHONGHUI ZHAO, YANING CHEN: "Research of Synchronization for Signals Cross Clock Domains in SoC Design", ELECTRONICS & PACKAGING, vol. 16, no. 1, 1 January 2016 (2016-01-01), pages 25 - 30, XP055956681, DOI: 10.16257/j.cnki.1681-1070.2016.0008
Attorney, Agent or Firm:
BEIJING SHENGFAN JIAHUA PATENT AGENCY (GENERAL PARTNERSHIP) (CN)
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