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Title:
LADDER ANNEALING PROCESS FOR INCREASING POLYSILICON GRAIN SIZE IN SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2022/204844
Kind Code:
A1
Abstract:
Semiconductor fabrication methods and semiconductor devices are disclosed. According to some aspects,, a memory device includes a memory stack having interleaved a plurality of conductive layers and a plurality of insulating layers on a substrate, and a channel structure extending vertically in the memory stack. The channel structure includes a semiconductor channel extending vertically in the memory stack and conductively connected to a source structure. The semiconductor channel includes polysilicon, and a grain size of the polysilicon ranges from 100 nm to 600 nm.

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Inventors:
LI TUO (CN)
PU HAO (CN)
LI LEI (CN)
WU CAIYU (CN)
Application Number:
PCT/CN2021/083492
Publication Date:
October 06, 2022
Filing Date:
March 29, 2021
Export Citation:
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Assignee:
YANGTZE MEMORY TECH CO LTD (CN)
International Classes:
H01L27/11582; H01L21/02; H01L21/324; H01L21/67; H01L27/1157
Foreign References:
US20180083028A12018-03-22
CN111197179A2020-05-26
CN111386607A2020-07-07
CN105226066A2016-01-06
CN110867451A2020-03-06
Attorney, Agent or Firm:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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