Title:
LAMINATED CERAMIC CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2023/243160
Kind Code:
A1
Abstract:
Provided is a laminated ceramic capacitor capable of suppressing electrical field concentration during voltage application while suppressing reduction of electrostatic capacitance. The laminated ceramic capacitor comprises: a laminate 10 having a plurality of dielectric layers 20 and a plurality of inner electrode layers 30; and first and second external electrodes 40A, 40B. The inner electrode layers 30 have a plurality of first and second inner electrode layers 31, 32 electrically connected to the first and second external electrodes 40A, 40B. The first and second inner electrode layers 31, 32 have a plurality of holes H having different area-equivalent diameters. When D99 denotes an area-equivalent diameter at which an accumulated value, in an accumulated distribution, of the area-equivalent diameter of the holes H exhibits 99%, and t denotes the thickness of each of the dielectric layers 20 interposed between the first and second inner electrode layers 31, 32, the thickness t of the dielectric layer 20 is at most 0.6 μm, and the following expression (1) is satisfied. (1): (Area-equivalent diameter D99)<0.1468×exp (6.7622×t)
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Inventors:
HIRAI TOMOAKI (JP)
Application Number:
PCT/JP2023/008535
Publication Date:
December 21, 2023
Filing Date:
March 07, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/30
Foreign References:
| JP2002075771A | 2002-03-15 | |||
| JP2013030753A | 2013-02-07 | |||
| JP2019114753A | 2019-07-11 |
Attorney, Agent or Firm:
KATO Ryuta et al. (JP)
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