Title:
LAYERED CERAMIC CAPACITOR, PRODUCTION METHOD FOR LAYERED CERAMIC CAPACITOR, AND MOUNTING STRUCTURE FOR LAYERED CERAMIC CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2023/189448
Kind Code:
A1
Abstract:
Provided is a layered ceramic capacitor that suppresses cracking and chipping of a laminate, even when stress is applied to a substrate on which the layered ceramic capacitor is mounted and the substrate bends. A layered ceramic capacitor according to the present invention comprises: a laminate that includes a plurality of ceramic layers, a plurality of first interior electrodes, and a plurality of second interior electrodes that are layered in a height direction and has a first principal surface and a second principal surface that are opposite in the height direction, a first end surface and a second end surface that are opposite in a length direction that is orthogonal to the height direction, and a first side surface and a second side surface that are opposite in a width direction that is orthogonal to the height direction and the length direction; a first end surface electrode that is formed on the first end surface and extends from the first end surface to cover a portion of the first principal surface, the second principal surface, the first side surface, and the second side surface; a second end surface electrode that is formed on the second end surface and extends from the second end surface to cover a portion of the first principal surface, the second principal surface, the first side surface, and the second side surface; a first side surface electrode that is formed on the first side surface and extends from the first side surface to cover a portion of the first principal surface and the second principal surface; and a second side surface electrode that is formed on the second side surface and extends from the second side surface to cover a portion of the first principal surface and the second principal surface. The first interior electrodes are connected to the first end surface electrode and the second end surface electrode, and the second interior electrodes are connected to the first side surface electrode and the second side surface electrode. The first end surface electrode and the second end surface electrode each include a first base electrode layer, a first plating electrode layer that is formed on the first base electrode layer, and a second plating electrode layer that is formed on the first plating electrode layer, and the first side surface electrode and the second side surface electrode each include a second base electrode layer, a third plating electrode layer that is formed on the second base electrode layer, a fourth plating electrode layer that is formed on the third plating electrode layer, a fifth plating electrode layer that is formed on the fourth plating electrode layer, and a sixth plating electrode layer that is formed on the fifth plating electrode layer.
Inventors:
NAKAMURA TOSHIYUKI (JP)
Application Number:
PCT/JP2023/009471
Publication Date:
October 05, 2023
Filing Date:
March 12, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/30; H01G2/06
Foreign References:
| JP2012156315A | 2012-08-16 | |||
| JP2020167231A | 2020-10-08 | |||
| JP2003077775A | 2003-03-14 |
Attorney, Agent or Firm:
KAWAMOTO, Takashi (JP)
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