Title:
LOGICAL CIRCUIT AND OPERATION METHOD IN DIGITAL CORRELATED DOUBLE SAMPLING
Document Type and Number:
WIPO Patent Application WO/2024/050718
Kind Code:
A1
Abstract:
A logic circuit (34) comprises a first logic circuit, a second logic circuit and a selector. The first logic circuit is configured to output a first operation result. The second logic circuit is configured to output a second operation result. The first operation result is a result of an exclusive-OR operation to input bits. The second operation result is a result of an exclusive-OR operation to input bits including the first operation result. In a code conversion mode, the selector outputs the second operation result, the input bits to the first logic circuit includes a bit in gray code representation and a bit in binary code representation of a second number-to-be-added, and the input bits to the second logic circuit further includes a bit in gray code representation of the second number-to-be-added. In an addition mode, the selector outputs a carry bit in an addition of a first number-to-be-added and the second number-to-be-added, the input bits to the first logic circuit includes a bit of the first number-to-be-added and a carry bit of a digit lower than the carry bit, and the input bits to the second logic circuit includes a bit of the second number-to-be added.
Inventors:
ISHII TAKAO (JP)
SHA YU (JP)
SHA YU (JP)
Application Number:
PCT/CN2022/117556
Publication Date:
March 14, 2024
Filing Date:
September 07, 2022
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H03K19/003
Foreign References:
| CN109561265A | 2019-04-02 | |||
| CN108881754A | 2018-11-23 | |||
| CN111182246A | 2020-05-19 | |||
| CN112422852A | 2021-02-26 | |||
| CN113411523A | 2021-09-17 | |||
| CN114982222A | 2022-08-30 | |||
| US20140266309A1 | 2014-09-18 |
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