Title:
LOW-RESOURCE MEMORY PROTECTION APPARATUS APPLIED TO RISC_V ARCHITECTURE
Document Type and Number:
WIPO Patent Application WO/2023/197823
Kind Code:
A1
Abstract:
A low-resource memory protection apparatus applied to an RISC_V architecture. The apparatus comprises an SoC module, an address merging module, an associative memory TLB module and a physical memory protection (PMP) module, which are connected in sequence, wherein the address merging module is used for merging an instruction acquisition address with a memory access address; the associative memory TLB module is used for realizing a quick search between a virtual address and a real physical address; the PMP module is used for realizing memory access permission and instruction execution information of the physical address; and the SoC module is used for executing an SoC program to realize memory protection. The apparatus has a simple structure, and greatly reduces an internal-resource application area for processing logic of a TLB and PMP, and the processing power consumption of a PMP structure, thereby having a relatively high practical value.
Inventors:
WANG SHUAI (CN)
JIANG KAI (CN)
ZHAO XINXIN (CN)
JIANG KAI (CN)
ZHAO XINXIN (CN)
Application Number:
PCT/CN2023/082094
Publication Date:
October 19, 2023
Filing Date:
March 17, 2023
Export Citation:
Assignee:
SHANDONG INSPUR SCIENCE RES INSTITUTE CO LTD (CN)
International Classes:
G06F12/14
Foreign References:
| CN114691552A | 2022-07-01 | |||
| CN113722246A | 2021-11-30 | |||
| CN113722247A | 2021-11-30 | |||
| CN1779663A | 2006-05-31 | |||
| US20050114586A1 | 2005-05-26 |
Attorney, Agent or Firm:
JINAN XINDA PATENT OFFICE CO., LTD. (CN)
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