MAGNETIC JUNCTION WITH SELF- ALIGNED PATTERNED SPIN ORBIT

COUPLING LAYER

BACKGROUND

[0001] Embedded memory with state retention can enable energy and computational efficiency. Leading spintronic memory uses spin Hall effect (SHE) to write to magnetic junctions such as magnetic tunnel junction (MTJ). SHE is the phenomena where a metal with a charge current running through it produces a spin current with a direction and magnetic polarization perpendicular to the charge current. This effect can be used to magnetically switch the magnetic polarization of the free magnetic layer of the MTJ. However, existing spintronic memory suffer from power inefficiencies due to, for example, geometrical misalignment of the conductor providing SHE and the MTJ.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a device having an in-plane magnetic tunnel junction (MTJ) stack coupled to a spin orbit coupling (SOC) interconnect.

[0004] Fig. 2 illustrates a cross-section of the SOC interconnect with electrons having their spins polarized in-plane and deflected up and down resulting from a flow of charge current.

[0005] Figs. 3A-B illustrate plots showing write energy-delay conditions for one transistor and one magnetic tunnel junction (MTJ) with spin Hall effect (SHE) material compared to traditional MTJs.

[0006] Figs. 4A-D illustrate three dimensional (3D) views of a device having a magnetic junction stack coupled to a spin Hall angle electrode aligned with the edges of the magnetic junction, according to some embodiments of the disclosure.

[0007] Fig. 5 illustrates a cross-section of a die layout having the device of Fig. 4D formed in metal 3 (M3) and metal 2 (M2) layer regions, according to some embodiments of the disclosure.

l [0008] Fig. 6 illustrates a cross-section of a die layout having the device of Fig. 4D formed in metal 2 (M2) and metal 1 (Ml) layer regions, according to some embodiments of the disclosure.

[0009] Fig. 7 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with self-aligned patterned spin Hall effect electrode and magnetic junction, according to some embodiments of the disclosure.

DETAILED DESCRIPTION

[0010] Some embodiments describe a spin Hall effect (SHE) MRAM (magnetic random access memory) with in-plane and/or out-of-plane magnetization where the conductor or material providing SHE is aligned (e.g., perfectly) with a magnetic junction (e.g., spin valve or magnetic tunnel junction (MTJ)). For example, width of the magnetic junction is aligned with the edges of the SHE interconnect to cause all current in the SHE interconnect to flow under the magnetic junction. In some embodiments, the process of alignment is a self-alignment process. In some embodiments, the entire stack of the device forming the magnetic junction is patterned into a line with dimension equal to the desired SHE conductor line (or interconnect) using standard lithography and etch processes. In some embodiments, a resist line is patterned perpendicular to the SHE conductor line and extends beyond the edges of the SHE conductor. In some embodiments, subsequent etch down to the bottom SHE conductor results in a remaining device stack that is perfectly aligned to the edges of the SHE conductor line.

[0011] There are many technical effects of the various embodiments. For example, in some embodiments, a perpendicular magnet switch is enabled using perpendicular magnet anisotropy (PMA) based magnetic devices (e.g., MRAM and logic) which comprises a switching mechanism based on spin orbit effects that generate perpendicular spin currents. The perpendicular magnet switch of some embodiments enables low programming voltages (or higher current for identical voltages) enabled by spin orbit coupling (SOC) for perpendicular magnetic memory and logic. By having the SHE conductor line perfectly aligned with the magnetic junction stack, all current through the SHE conductor line is used to generate spin current for switching a free magnet layer of the magnetic junction. For example, there is no unused current flowing along the sides of the SHE conductor line and away from the free magnet layer of the magnetic junction. As such, a memory bit-cell comprising the SHE conductor line and the magnetic junction is power efficient. [0012] The perpendicular magnet switch, of some embodiments, results in lower write error rates which enable faster MRAM (e.g., write time of less than 10 ns). The perpendicular magnet switch of some embodiments decouple write and read paths to enable faster read latencies. The perpendicular magnet switch of some embodiments uses significantly smaller read current through the MTJ and provides improved reliability of the tunneling oxide and MTJs. For example, less than 10 μΑ compared to 100 μΑ for nominal write is used by the perpendicular magnet switch of some embodiments. Other technical effects will be evident from the various figures and embodiments.

[0013] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0014] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0015] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0016] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value.

[0017] Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0018] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0019] The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descripti ve purposes and not necessarily for describing permanent relative positions. For the purposes of present disclosure the terms "spin" and "magnetic moment" are used equivalent!}' ^' . More rigorously, the direction of the spin is opposite to that of the magnetic moment, and the charge of the particle is negative (such as in the case of electron).

[0020] Fig. 1 illustrates device 100 having an in-plane magnetic tunnel junction

(MTJ) stack coupled to a spin orbit coupling interconnect. Here, the stack of layers having MTJ 121 is coupled to electrode 122 formed of spin Hall effect (SHE) or SOC material, where the SHE material converts charge current Iw (or write current) to spin current Is. Spin Hall effect, in general, is a phenomena where a metal with a charge current running through it will produce a spin current with a direction and magnetic polarization perpendicular to the charge current. This effect can be used to magnetically switch the magnetic polarization of the free or memory layer of a magnetic storage device using a charge current.

[0021] Device 100 forms a three terminal memory cell with SHE induced write mechanism and MTJ based read-out. Device 100 comprises MTJ 121, SHE Interconnect or electrode 122, and non-magnetic metal(s) 123a/b. In one example, MTJ 121 comprises layers 121a, 121b, and 121c. In some embodiments, layers 121a and 121c are ferromagnetic layers. In some embodiments, layers 121a and 121c are paramagnet layers. In some embodiments, layer 121b is a metal or a tunneling dielectric. One or both ends along the horizontal direction of SHE Interconnect 122 is formed of non-magnetic metals 123a/b. Additional layers 121d, 121e, 121f, and 121g can also be stacked on top of layer 121c. In some embodiments, layer 121g is non-magnetic metal electrode.

[0022] A wide combination of materials can be used for material stacking of MTJ

121. For example, the stack of layers 121a, 121b, 121c, 121d, 121e, 121f, and 121g are formed of materials which include: Co _x FeyB _z , MgO, Co _x FeyB _z , Ru, Co _x FeyB _z , IrMn, and Ru, respectively, where 'x,' 'y,' and 'z' are fractions of elements in the alloys. Other materials may also be used to form MTJ 121. MTJ 121 stack comprises free magnetic layer 121a, MgO tunneling oxide 121b, a fixed magnetic layer 121c/d/e which is a combination of CoFe, Ru, and CoFe layers, respectively, referred to as Synthetic Anti-Ferromagnet (SAF), and an Anti-Ferromagnet (AFM) layer 121f. The SAF layer has the property, that the

magnetizations in the two CoFe layers are opposite, and allows for cancelling the dipole fields around the free magnetic layer such that a stray dipole field will not control the free magnetic layer.

[0023] In some embodiments, materials for the free and fixed magnetic layers (121a and 121c, respectively) are paramagnets. Paramagnets are non-ferromagnetic elements with strong paramagnetism materials which have high number of unpaired spins but are not room temperature ferromagnets.

[0024] In some embodiments, the free and fixed magnetic layers (121a and 121c, respectively) comprise a material which include one or more of: Platinum (Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnO (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy20 (dysprosium oxide), Erbium (Er), EnO (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd203), FeO and Fe203 (Iron oxide), Neodymium (Nd), Nd203 (Neodymium oxide), KO2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), S1T12O3 (samarium oxide), Terbium (Tb), Tb203 (Terbium oxide), Thulium (Tm), T1T12O3 (Thulium oxide), or V2O3 (Vanadium oxide).

[0025] In some embodiments, the free and fixed magnetic layers (121a and 121c, respectively) comprise dopants which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, and Yb. The relaxation time of a paramagnet is enhanced (e.g., made shorter) by doping with materials with stronger dissipation elements to promote Spin- lattice relaxation time (Ti) and Spin-spin relaxation time (T2). Here, the term "Spin-lattice relaxation time (Ti)" generally refers to the mechanism by which the component of the magnetization vector along the direction of the static magnetic field reaches thermodynamic equilibrium with its surroundings. Here, the term "Spin-spin relaxation time (T ₂ )" generally refers to a spin-spin relaxation is the mechanism by which, the transverse component of the magnetization vector, exponentially decays towards its equilibrium value.

[0026] In some embodiments, the free and fixed magnetic layers (121a and 121c, respectively) are formed of CFGG (i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). In some embodiments, magnets 121a/c are formed from Heusler alloys. Heusler alloys are ferromagnetic metal alloys based on a Heusler phase. Heusler phases are intermetallic with certain composition and face-centered cubic crystal structure. The ferromagnetic property of the Heusler alloys are a result of a double-exchange mechanism between neighboring magnetic ions.

[0027] SHE Interconnect 122 (or the write electrode) include one or more of β-

Tantalum (β-Ta), Ta, β-Tungsten (β-W), W, Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the Periodic Table which may exhibit high spin orbit coupling. SHE Interconnect 122 transitions into high conductivity non-magnetic metal(s) 123a/b to reduce the resistance of SHE

Interconnect 122. The non-magnetic metal(s) 123a/b include one or more of: Cu, Co, a-Ta, Al, CuSi, or NiSi.

[0028] In one case, the magnetization direction of the fixed magnetic layer 121c is perpendicular relative to the magnetization direction of the free magnetic layer 121a (e.g., magnetization directions of the free and fixed magnetic layers are not parallel, rather they are orthogonal). For example, the magnetization direction of free magnetic layer 121a is in-plane while the magnetization direction of fixed magnetic layer 121c is perpendicular to the in- plane. In another case, the magnetization direction of fixed magnetic layer 121a is in-plane while the magnetization direction of free magnetic layer 121c is perpendicular to the in-plane.

[0029] The thickness of a ferromagnetic layer (e.g., fixed or free magnetic layer) may determine its equilibrium magnetization direction. For example, when the thickness of the ferromagnetic layer 121a/c is above a certain threshold (depending on the material of the magnet, e.g. approximately 1.5 nm for CoFe), then the ferromagnetic layer exhibits magnetization direction which is in-plane. Likewise, when the thickness of the ferromagnetic layer 121a/c is below a certain threshold (depending on the material of the magnet), then the ferromagnetic layer 121a/c exhibits magnetization direction which is perpendicular to the plane of the magnetic layer.

[0030] Other factors may also determine the direction of magnetization. For example, factors such as surface anisotropy (depending on the adjacent layers or a multi -layer composition of the ferromagnetic layer) and/or crystalline anisotropy (depending on stress and the crystal lattice structure modification such as FCC (face centered cubic lattice), BCC (body centered cubic lattice), or Llo-type of crystals, where Llo is a type of crystal class which exhibits perpendicular magnetizations), can also determine the direction of magnetization.

[0031] In this example, the applied current I _w is converted into spin current Is by SHE

Interconnect 122. This spin current switches the direction of magnetization of the free layer and thus changes the resistance of MTJ 121. However, to read out the state of MTJ 121, a sensing mechanism is needed to sense the resistance change.

[0032] The magnetic cell is written by applying a charge current via SHE

Interconnect 122. The direction of the magnetic writing (in the free magnet layer 121a) is decided by the direction of the applied charge current. Positive currents (e.g., currents flowing in the +y direction) produce a spin injection current with transport direction (along the +z direction) and spins pointing to the +x direction. The injected spin current in turn produces spin torque to align the free magnet 121a (coupled to the SHE layer 122 of SHE material) in the +x direction. Negative currents (e.g., currents flowing in the -y direction) produce a spin injection current with transport direction (along the +z direction) and spins pointing to the -x direction. The injected spin current in-tum produces spin torque to align the free magnet 121a (coupled to the SHE material of layer 122) in the -x direction. In some embodiments, in materials with the opposite sign of the SHE/SOC effect, the directions of spin polarization and thus of the free layer magnetization alignment are reversed compared to the above.

[0033] Inefficiency can arise when the length or radius of the magnetic junction 121 on SHE Interconnect 122 is not the same as the width of SHE Interconnect 122. This is illustrated in Fig. 2 where the charge current that does not flow under magnetic junction 121 has no effect on magnetic junction 121 and represents unnecessary current resulting in higher power needed to switch magnetic junction 121. Therefore, the switching current and power can be minimized if the length of the device is equal to the width of the spin metal 122, in accordance with some embodiments.

[0034] Fig. 2 illustrates a cross-section view 200 of the spin orbit coupling interconnect with electrons having their spins polarized in-plane and deflected up and down resulting from a flow of charge current. It is pointed out that those elements of Fig. 2A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. [0035] In this example, positive charge current 201 a and 201b represented by Jc produces spin-front (e.g., in the +x direction) polarized current 202 and spin-back (e.g., in the -x direction) polarized current 203. The injected spin current / _s generated by a charge current I _W in the write electrode 122 is given by:

= PSHE w, t, _sf , θ _5ΗΕ ) (ζ χ ζ) . . . (1)

where, the vector of spin current / _s = / _† — /j, is the difference of currents with spin along and opposite to the spin polarization direction, z is the unit vector perpendicular to the interface, P _SHE is the spin Hall injection efficiency which is the ratio of magnitude of transverse spin current to lateral charge current, w is the width of the magnet, t is the thickness of the SHE Interconnect 122, _S f is the spin flip length in SHE Interconnect 122, Θ _5ΗΕ is the spin Hall angle for SHE Interconnect 122 to free magnet layer interface. The injected spin angular momentum responsible for the spin torque given by:

[0036] The generated spin up and down currents 202/203 (e.g., ] _s 204) are described as a vector cross-product given by:

[0037] This spin to charge conversion is based on Tunnel Magneto Resistance (TMR) which is highly limited in the signal strength generated. The TMR based spin to charge conversion has low efficiency (e.g., less than one).

[0038] The positive charge currents 201 a and 201b represented by J _c include charge current 201 a which remains unused in the sense that it produces no switching impact on free magnet layer 121a of magnetic junction 121. Here, charge current 201b flows under free magnet layer 121a of magnetic junction 121 , and this charge current switches free magnet layer 121a of magnetic junction 121. The unused current 201 a results in higher power needed to switch free magnet layer 121a of magnetic junction 121 because the unused current 201a is wasted current. In some embodiments, SHE Interconnect 122 is fabricated such that edges (square or tangents of a round shape) of magnetic junction 121 are aligned with the edges of SHE Interconnect 122.

[0039] Here, the spin polarization direction for the SOC materials of Fig. 1 are in- plane, and so a perpendicularly magnetized free magnet layer coupled to SOC interconnect 122 can be switched inefficiently and in the presence of a significant external magnetic field. This means forming devices (e.g., logic and memory) with perpendicular magnetic anisotropy (PMA) are a challenge with SOC interconnect 122. However, interconnect 122 with SOC material can also produce spin polarization perpendicular to the plane of the device. For example, interconnect 122 with SOC material that produces Rashba-Bychkov effect can be used with perpendicular magnet 121a.

[0040] In one such embodiment, the free magnetic layer 121a has Perpendicular

Magnetic Anisotropy (PMA). Here, perpendicularly magnetized free magnet refers to a magnet having magnetization which is perpendicular to the plane of the magnet as opposed to in-plane magnet that has magnetization in a direction along the plane of the magnet.

[0041] In some embodiments, the free perpendicular magnet layer 121a of the magnetic junction (e.g., spin valve or MTJ 121), which is coupled to interface normal spin orbit material based interconnect 122, comprises one or a combination of materials which include one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Gamet (YIG). In some embodiments, the Heusler alloy is a material which includes one or more of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[0042] In some embodiments, the free perpendicular magnet layer 121a of the magnetic junction (e.g., spin valve or MTJ 121) is formed of a stack of materials, wherein the materials for the stack include one or more of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn _x Ga _y ; Materials with Llo symmetry; or materials with tetragonal crystal structure.

[0043] Llo is a crystallographic derivative structure of a FCC structure and has two of the faces occupied by one type of atom and the corner and the other face occupied with the second type of atom. When phases with the Llo structure are ferromagnetic the

magnetization vector usually is along the [0 0 1] axis of the crystal. Examples of materials with Llo symmetry include CoPt and FePt. Examples of materials with tetragonal crystal structure and magnetic moment are Heusler alloys such as CoFeAl, MnGe, MnGeGa, and MnGa. In some embodiments, the free magnet layer of the magnetic junction (e.g., spin valve or MTJ 121) is formed of a single layer of one or more materials. In some

embodiments, the single layer is formed of MnGa.

[0044] In some embodiments, the fixed perpendicular magnet layer 121c is formed with interfacial PMA, multi -interface PMA, magnetic crystalline anisotropy or multi-layer PMA. In some embodiments, the free perpendicular magnet layer 121a is formed with interfacial PMA, multi-interface PMA, magnetic crystalline anisotropy or multi-layer PMA. In some embodiments, TMR is used for memory readout from PMA-MTJ 121. In some embodiments, the magnet with PMA is formed of a stack of materials, wherein the materials for the stack include one or more of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn _x Ga _y ; Materials with Llo symmetry; or materials with tetragonal crystal structure. In some embodiments, the magnet with PMA is formed of a single layer of one or more materials. In some embodiments, the single layer comprises Mn and Ga. For example, the signal layer comprises MnGa.

[0045] In some embodiments, the perpendicular magnets of layer 121a of the magnetic junction (e.g., spin valve or MTJ 121) are formed with a sufficiently high anisotropy (indicated by an effective anisotropy magnetic field Hk) and sufficiently low saturated magnetization (M _s ) to increase injection of spin currents. Saturated magnetization Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Here, sufficiently low M _s refers to M _s less than 200 kA/m (kilo- Amperes per meter). Anisotropy Hk generally refers to the material property which is directionally dependent. Materials with high Hk are materials with material properties that are highly directionally dependent. Here, sufficiently high Hk in context of Heusler alloys is considered to be greater than 2000 Oe (Oersted).

[0046] In some embodiments, interconnect 122 with SOC material comprises multiple layers. In some embodiments, interconnect 122 with SOC comprises a first interface layer comprising a material which includes one of: Ag, Cu, Au, or Al. In some embodiments, interconnect 122 with SOC comprises a bulk layer adjacent to the first interface layer, wherein the bulk layer comprises a material which includes one of: Ta, Hf, W, Pt, Bi; Ag doped with Ta, Hf, W, Pt, Bi, or Ir; Al doped with Ta, Hf, W, Pt, Bi, or Ir; Cu doped with Ta, Hf, W, Pt, Bi, or Ir; and Au doped with Ta, Hf, W, Pt, Bi, or Ir. In some embodiments, interconnect 122 with SOC comprises a second interface layer adjacent to the bulk layer, wherein the second interface layer is formed of a different material than the first interface layer, wherein the different material for the second interface layer includes one of: Ag, Cu, Al, or Au. In some embodiments, interconnect 122 with SOC comprises a metal layer adjacent to the second interface layer, wherein the metal layer comprises a material which includes one of: Bi, Pb, or chalcogenide material.

[0047] In some embodiments, the chalcogenide material includes one of: TiSe2,

MoSe2, WSe2, S1S2, B2S3, Sb2S3, Ta ₂ S, RKS? or semiconductors of the type MX2, wi th 'JVP being a transition metal and 'X' being an achalcogen. In some embodiments, 'M' includes one of: Mo and W, and wherein 'X' is includes one of of: S, Se, or Te.

[0048] Figs. 3A-B illustrate plots 300 and 320, respectively, showing write energy- delay conditions for one transistor and one magnetic tunnel junction (MTJ) with spin Hall effect (SHE) material compared to traditional MTJs.

[0049] Here, the energy-delay trajectory of SHE and MTJ devices are compared for in-plane magnet switching as the applied write voltage is varied. The energy-delay relationship (for in-plane switching) can be written as:

[0050] Where R _wr ue^ ^s the write resistance of the device (resistance of SHE electrode

122 or resistance of MTJ-P or MTJ-AP, where MTJ-P is a MTJ with parallel magnetizations while MTJ-AP is an MTJ with anti-parallel magnetizations, μ ₀ is vacuum permeability, e is the electron charge. The equation shows that the energy at a given delay is directly proportional to the square of the Gilbert damping a. Here the characteristic time, τ ₀ =

M Ve

^S 11 P _iB ^var ^ ^{es as tne s} P ^m P ^oia rization varies for various SHE metal electrodes (e.g., 303, 304, 305). Plot 300 shows five curves 301, 302, 303, 304, and 305. Curves 301 and 302 show write energy-delay conditions using traditional MTJ devices without SHE material. For example, curve 301 shows the write energy-delay condition causes by switching a magnet from anti-parallel (AP) to parallel (P) state, while curve 302 shows the write energy-delay condition causes by switching a magnet from P to AP state. Curves 302, 303, and 304 show write energy-delay conditions of an MTJ with SHE material. Clearly, write energy-delay conditions of an MTJ with SHE material is much lower than write energy-delay conditions of an MTJ without SHE material. While write energy-delay of an MTJ with SHE material improves over a traditional MTJ without SHE material, further improvement in write energy- delay is desired.

[0051] Fig. 3B illustrates plot 320 comparing reliable write times for spin Hall

MRAM and spin torque MRAMs. There are three cases considered in plot 320. Waveform 321 is the write time for in-plane MTJ, waveform 322 is the write time for PMA MTJ, and waveform 324 is the write time for spin Hall MTJ. All the cases considered in Fig. 3B assume a 30 X 60 nm magnet with 40 kT energy barrier and 3.5 nm SHE electrode thicknesses. The energy-delay trajectories of the devices are obtained assuming a voltage sweep from 0-0.7 V in accordance to voltage restrictions of scaled CMOS. The energy-delay trajectory of the SHE-MTJ devices exhibits broadly two operating regions A) Region 1 where

M Ve

the energy-delay product is approximately constant (τ _α < ^s /j μ _β )' ¾ Region 2 where

M Ve

the energy is proportional to the delay τ _α > ^s /j p The two regions are separated by energy minima at τ _ορί = ^ ^s ^ ^e j ^ ^ where minimum switching energy is obtained for the spin torque devices.

[0052] The energy-delay trajectory of the STT-MTJ devices is limited with a minimum delay of 1 ns for in-plane devices at 0.7 V maximum applied voltage, the switching energy for P-AP and AP-P are in the range of 1 pJ/write. In contrast, the energy-delay trajectory of SHE-MTJ (in-plane anisotropy) devices can enable switching times as low as 20 ps (β-W with 0.7 V, 20 fj/bit) or switching energy as small as 2 fj (β-W with 0.1 V, 1.5 ns switching time).

[0053] Figs. 4A-D illustrate 3D views 400, 420, 430, and 440, respectively, of a device having an magnetic junction stack coupled to a spin Hall electrode with edges aligned with the edges of the magnetic junction, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 4A-B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0054] View 400 shows the deposition and patterning of device stack (e.g., 121 a-g), including the bottom layer spin-metal 122. In some embodiments, the device stack is rectangular or square in shape. However, the embodiments are also applicable to round (or dot) shaped device stack with portions for round device in direct alignment with spin-metal 122. For example, tangents for round device may align directly with the edges of the spin- metal 122. The width of the patterned spin metal 122 is patterned to be the desired length of the spin device. Here, label for spin metal is same as the label for spin interconnect 122 of Figs. 1-2 because material wise they are the same. However, at least two edges of spin metal 122 in Figs. 4A-4D align with at least two edges of the magnetic junction 121.

[0055] View 420 shows the forming of patterned resist line 421 to be perpendicular and on top of device stack. Any known suitable resist (or photo-resist) material can be used for patterned resist line 421. The width of the resist line 421 is equal to the desired width of the device. In some embodiments, the length of the resist line 421 is made larger than the length of spin-metal 122. [0056] View 430 shows etching down of the device stack to the spin-metal layer 122.

The patterned spin-metal layer is left in place to serve as an interconnect to the device. Any suitable etch process (dry etch or wet etch) can be used. In some embodiments, the etch stops at detecting of the material used for spin-metal layer 122. Any suitable end point detection can be used.

[0057] View 440 shows removing of resist line 421. Any standard resist clean process can be used. The resulting product is a perfectly aligned device with remaining spin metal that can serve as interconnects. For example, Edge 1 and Edge 2 of spin- metal 122 is aligned with the device width. As such, currents 201 a are eliminated and all charge current flows under device 121 (e.g., charge current 201b) to switch free magnet 121 a.

[0058] Fig. 5 illustrates a cross-section 500 of a die layout having the device of Fig.

4D formed in metal 3 (M3) and metal 2 (M2) layer regions, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0059] Cross-section 500 illustrates an active region having an n-type transistor MN comprising diffusion region 501, a gate terminal 502, drain terminal 504, and source terminal 503. The source terminal 503 is coupled to SL (source line) via poly or via, where the SL is formed on Metal 0 (M0). In some embodiments, the drain terminal 504 is coupled to MOa (also metal 0) through via 505. The drain terminal 504 is coupled to spin Hall electrode 122 through Via 0-1 (e.g., via connecting metal 0 to metal 1 layers), metal 1 (Ml), Via 1 -2 (e.g., via connecting metal 1 to metal 2 layers), and Metal 2 (M2). In some embodiments, the magnetic junction (e.g., MTJ 121 or spin valve) is formed in the metal 3 (M3) region. In some embodiments, the perpendicular free magnet layer of the magnetic junction (MTJ 121 or spin valve) couples to spin Hall electrode 122. In some embodiments, the fixed magnet layer of magnetic junction couples to the bit-line (BL) via spin Hall electrode 122 through Via 3-4 (e.g., via connecting metal 4 region to metal 4 (M4)). In this example, bit-line is formed on M4.

[0060] In some embodiments, transistor MN is formed in the frontend of the die while spin Hall electrode 122 is located in the backend of the die. Here, the term "backend" generally refers to a section of a die which is opposite of a "frontend" and where an IC (integrated circuit) package couples to IC die bumps. For example, high level metal layers (e.g., metal layer 6 and above in a ten metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die. Conversely, the term "frontend" generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 and below in the ten metal stack die example). In some embodiments, spin Hall electrode 122 is located in the backend metal layers or via layers for example in Via 3. In some embodiments, the electrical connectivity to the device is obtained in layers MO and M4 or Ml and M5 or any set of two parallel interconnects.

[0061] Fig. 6 illustrates cross-section 600 of a die layout having the device of Fig. 4D formed in metal 2 and metal 1 layer regions, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Compared to Fig. 5, here the magnetic junction (e.g., MTJ 121 or spin valve) is formed in the metal 2 region and/or Via 1-2 region. In some embodiments, the spin Hall electrode 122 with field assist is formed in the metal 1 region.

[0062] Fig. 7 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with self-aligned patterned spin Hall effect electrode and magnetic junction, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0063] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[0064] Fig. 7 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0065] In some embodiments, computing device 1600 includes first processor 1610 with device 440, according to some embodiments discussed. Other blocks of the computing device 1600 may also device 440, according to some embodiments. The various

embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0066] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors,

microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0067] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0068] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user. [0069] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0070] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0071] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0072] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0073] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0074] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0075] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0076] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0077] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0078] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0079] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0080] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0081] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0082] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0083] Example 1 is an apparatus which comprises: a magnetic junction having a free magnet layer; and an interconnect adjacent to the free magnet layer, wherein the interconnect includes a material to provide spin orbit coupling to the free magnet layer, wherein at least two edges of the free magnet layer are aligned with at least two edges of the interconnect, respectively.

[0084] Example 2 includes all features of example 1, wherein the free magnet layer has a dimension extending along a plane of the apparatus, wherein the interconnect has a dimension extending along the plane, and wherein the dimension of the free magnet is equal to the dimension of the interconnect.

[0085] Example 3 includes all features of example 1, wherein the free magnet layer has perpendicular magnetic anisotropy (PMA) such that the free magnet layer has anisotropy axis perpendicular to a plane of a device.

[0086] Example 4 includes all features of example 1, wherein the interconnect is to generate spin Hall effect (SHE).

[0087] Example 5 is according to any one of examples 1 to 4, wherein the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).

[0088] Example 6 is according to any one of examples 1 to 5, wherein the free magnet layer comprises one or a combination of materials which include one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[0089] Example 7 includes all features of example 6, wherein the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb,

Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn,

Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[0090] Example 8 is according to any one of examples 1 to 4, wherein the free magnet layer is part of a stack of materials, wherein the materials for the stack include one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; or Mn _x Ga _y .

[0091] Example 9 is according to any one of examples 1 to 4, wherein the free magnet layer comprises a single layer of one or more materials.

[0092] Example 10 includes all features of example 9, wherein the single layer includes: Mn and Ga.

[0093] Example 11 is according to any one of examples 1 to 4, wherein the interconnect include one or more of β-Tantalum (β-Ta), Ta, β-Tungsten (β-W), W, Pt, or Copper (Cu) doped with elements from 3d, 4d, 5d and 4f, 5f periodic groups.

[0094] Example 12 is according to any one of claims 1 to 4, wherein the interconnect comprises: a first interface layer comprising a material which includes one of: Ag, Cu, Au, or Al; a bulk layer adjacent to the first interface layer, wherein the bulk layer comprises a material which includes one of: Ta, Hf, W, Pt, Bi; Ag doped with Ta, Hf, W, Pt, Bi, or Ir; Al doped with Ta, Hf, W, Pt, Bi, or Ir; Cu doped with Ta, Hf, W, Pt, Bi, or Ir; and Au doped with Ta, Hf, W, Pt, Bi, or Ir; a second interface layer adjacent to the bulk layer, wherein the second interface layer is formed of a different material than the first interface layer, wherein the different material for the second interface layer includes one of: Ag, Cu, Al, or Au; and a metal layer adjacent to the second interface layer, wherein the metal layer comprises a material which includes one of: Bi, Pb, or chalcogenide material.

[0095] Example 13 includes all features of example 12, wherein the chalcogenide material includes one of of: TiSe2, MoSe2, WSe2, S1S2, B2S3, Sb2S3, Ta ₂ S, Re2S? or and semiconductors of the type MX2, with 'M' being a transition metal and 'X' being an achalcogen.

[0096] Example 14 includes all features of example 13, wherein ^" M ^" includes one of:

Mo and W, and wherein 'X" is includes one of of: S, Se, or Te.

[0097] Example 15 is a system which comprises: a memory; a processor coupled to the memory, the processor having a spin wave switch, which comprises an apparatus according to any one of apparatus examples 1 to 14; and a wireless interface to allow the processor to communicate with another device.

[0098] Example 16 is a method which comprises: forming a magnetic junction having a free magnet layer; and forming an interconnect adjacent to the free magnet layer, wherein the interconnect includes a material to provide spin orbit coupling to the free magnet layer, wherein at least two edges of the free magnet layer are aligned with at least two edges of the interconnect, respectively.

[0099] Example 17 includes all features of example 16, wherein the free magnet layer has a dimension extending along a plane of an apparatus, wherein the interconnect has a dimension extending along the plane, and wherein the dimension of the free magnet is equal to the dimension of the interconnect.

[00100] Example 18 includes all features of example 16, wherein the free magnet layer has perpendicular magnetic anisotropy (PMA) such that the free magnet layer has anisotropy axis perpendicular to a plane of a device.

[00101] Example 19 includes all features of example 16, wherein the interconnect is to generate spin Hall effect (SHE).

[00102] Example 20 is according to any one of examples 16 to 19, wherein the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).

[00103] Example 21 is according to any one of claims 16 to 20, wherein the interconnect include one or more of β-Tantalum (β-Ta), Ta, β-Tungsten (β-W), W, Pt, or

Copper (Cu) doped with elements from 3d, 4d, 5d and 4f, 5f periodic groups.

[00104] Example 22 is according to any one of examples 16 to 20, wherein the free magnet layer comprises one or a combination of materials which include one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[00105] Example 23 includes all features of example 22, wherein the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb,

Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn,

Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00106] Example 24 is according to any one of examples 16 to 20, wherein the free magnet layer is part of a stack of materials, wherein the materials for the stack include one of:

Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W,

CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and

MgO; or Mn _x Ga _y .

[00107] Example 25 is according to any one of examples 16 to 20, wherein the free magnet layer comprises a single layer of one or more materials.

[00108] Example 26 includes all features of example 25, wherein the single layer includes: Mn and Ga.

[00109] Example 27 is according to any one of examples 16 to 24, wherein forming the interconnect comprises: forming a first interface layer comprising a material which includes one of: Ag, Cu, Au, or Al; forming a bulk layer adjacent to the first interface layer, wherein the bulk layer comprises a material which includes one of: Ta, Hf, W, Pt, Bi; Ag doped with Ta, Hf, W, Pt, Bi, or Ir; Al doped with Ta, Hf, W, Pt, Bi, or Ir; Cu doped with Ta, Hf, W, Pt, Bi, or Ir; and Au doped with Ta, Hf, W, Pt, Bi, or Ir; forming a second interface layer adjacent to the bulk layer, wherein the second interface layer is formed of a different material than the first interface layer, wherein the different material for the second interface layer includes one of: Ag, Cu, Al, or Au; and forming a metal layer adjacent to the second interface layer, wherein the metal layer comprises a material which includes one of: Bi, Pb, or chalcogenide material.

[00110] Example 28 includes all features of example 27, wherein the chalcogenide material includes one of of: TiSe2, MoSe2, WSe2, S1S2, B2S3, Sb2S3, Ta ₂ S, ReaS? or and semiconductors of the type MX?., with ¾! ^' being a transition metal and 'X' being an achalcogen.

[00111] Example 29 includes all features of example 28, wherein 'M' includes one of:

Mo and W, and wherein 'X' is includes one of of; S, Se, or Te.

[00112] Example 30 is a method which comprises: depositing a material that exhibits spin coupling effect; depositing a stack of layers forming a magnetic junction, wherein the stack of layers includes a free magnet layer which is adjacent to the material exhibiting spin orbit coupling; depositing a resist over the stack of layers; patterning the resist into a resist line having a width which is a width of a device having the stack of layers and the material that exhibits spin coupling effect; and etching, around the resist line, the stack of layers down to the material that exhibits spin coupling effect.

[00113] Example 31 includes all features of example 30, and comprises removing the resist line.

[00114] Example 32 includes all features of example 31, and comprises coupling a transistor to the material that exhibits spin coupling effect.

[00115] Example 33 is according to any one of examples 30 to 32, wherein the device is a magnetic junction, and wherein the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).

[00116] Example 34 includes all features of example 33, wherein the free magnet layer comprises one or a combination of materials which include one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[00117] Example 35 includes all features of example 34, wherein the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00118] Example 36 is according to any one of examples 30 to 35, wherein the interconnect include one or more of β-Tantalum (β-Ta), Ta, β-Tungsten (β-W), W, Pt, or Copper (Cu) doped with elements from 3d, 4d, 5d and 4f, 5f periodic groups.

[00119] Example 37 is according to any one of examples 30 to 36, wherein the stack of layers include one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; or Mn _x Ga _y .

[00120] Example 38 includes all features of example 37, wherein the free magnet layer comprises a single layer of one or more materials.

[00121] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.