Description MANUFACTURING METHOD AND POWER SEMICONDUCTOR DEVICE A manufacturing method for a power semiconductor device is provided. Further, a power semiconductor device is also provided. Documents US 2019/0296146 A1 and US 2002/0034852 A1 refer to semiconductor devices with differently doped regions. A problem to be solved is to provide a power semiconductor device having improved electric behaviour. This object is achieved, inter alia, by a manufacturing method any by a power semiconductor device as specified in the independent patent claims. Further exemplary embodiments are specified in the dependent patent claims. For example, in the method described herein low-energy electron radiation is used in order to improve flat band voltage, V _FB , and reduce carbon, C, defects at an oxide-SiC interface, for example, at a SiO ₂ /SiC interface. In at least one embodiment, the method is for producing a power semiconductor device and comprises the following steps, for example, in the stated sequence: - providing a semiconductor body based on a carbon-containing semiconductor material, like SiC, - irradiating at least one first portion of a top side of the semiconductor body with low-energy electron radiation, and - producing an electrical insulation layer at least in the at least one irradiated first portion. For example, the low- energy electron radiation has a kinetic energy of at least 116 keV and at most 210 keV, by means of the low-energy electron radiation in the at least one first portion carbon atoms are moved from the top side into the semiconductor body so that after irradiating the at least one first portion, ^{there the semiconductor body has a layer of Si} _0.5+x ^C _0.5-x ^, wherein x is at least 0.001 and is at most 0.1, said layer has a thickness of at least 10 nm and of at most 0.2 µm, and the electrical insulation layer is produced by thermal growth. Despite the high bulk mobility of SiC, low inversion-channel mobilities µ have been reported in SiC metal-oxide- semiconductor field-effect transistors, MOSFETs, leading to a much higher on-state resistance than what is expected from bulk SiC properties. This discrepancy has been attributed to the large density of interface states, D _it , at an SiO ₂ /SiC interface, which is one to three orders of magnitude higher than in the case of an SiO ₂ /Si interface. The nature of D _it close to the edge of the conduction band is generally attributed to the presence of C-related defects and intrinsic oxide acceptor defects. The presence of carbon in the SiC epilayer is due to injection during oxidation. The injected C atoms form clusters that give rise to acceptor levels close to the conduction band. These levels shorten charge carriers’ lifetime and act as scattering centers, thus reducing µ. In order to improve the electronic properties of a SiC MOSFET, the concentration of C defects, D _it , at the SiO ₂ /n- type 4H-SiC interface should be reduced. In the method described herein, pre-oxidation low-energy electron irradiation for defect reduction at the SiO ₂ /n-type 4H-SiC interface is used. For n-type channel MOSFETs, different ways of reducing D _it are possible, such as the post-oxidation annealing, POA, and pre-oxidation implantation, POI. POA in either N ₂ O or POCl ₃ ambient, or POI, by either N, P or Sb donor impurities, results in a decrease of D _it in the upper part of SiC band _{gap (10} ¹¹ _cm ^-2 _eV ^-1 _{for POA, low 10} ¹² _cm ^-2 _eV ^-1 _{for POI) and increase of µ (90 cm} ² _V ^-1 _s ^-1 _{for POA, 20 cm} ² _V ^-1 _s ^-1 _{to 100} cm ² V ^-1 s ^-1 for POI). The reason for the reduction of D _it , and subsequent µ increase, has been explained in terms of N or P atoms passivating the C-clusters or in terms of counter- doping. Nevertheless, both POA and POI have some drawbacks: the concentration of incorporated N or P is difficult to control by POA and flat-band voltage, V _FB , shift, due to the introduction of N or P or Sb in SiO ₂ , can occur. In addition, since P is more easily incorporated into SiC than N, normally-on devices can be obtained. One idea of the present method is, inter alia, to employ low energy electron irradiation in order to create a C-poor, that is, a layer rich of voids of C, also referred to as a V _C -rich layer. This will act as a sink for C, leading to an improved V _FB and the reduction of D _it at the SiO ₂ /4H-SiC interface. In order to produce V _C , low energy electron irradiation is employed, for example, with an energy between 116 keV and 210 keV. This is the minimum energy required in order to produce the displacement of C atoms, that is, V _C . In this way, virtually no other defects will be formed, either complex or Si-related, as occur after impurity implantation or higher energy electron irradiation. Following irradiation, [V _C ] increases and the displaced carbon interstitial (C _I )atoms will be in-diffused deep in the bulk by thermal annealing treatment at, for example, at most 500 °C. Although C _I is mobile even at room temperature, a thermal treatment can prevent C atoms displaced by irradiation from clustering during oxidation. For an Al implanted n-type 4H-SiC epilayer, [V _C ] is 6 x 1015 cm ^-3 . After dry oxidation at 1150 °C for 2 h, [V _C ] becomes _{3 x 10} ¹⁵ _cm ^-3 _{, meaning that about 3 x 10} ¹⁵ _cm ^-3 _{[CI] have} been injected during oxidation. This means that prior to the formation of, for example, a 65 nm thick SiO ₂ , the as-grown n-type epilayer should be irradiated with an electron dose such that [V _C ] is at least 3 x 10 ¹⁵ _cm ^-3 _{, for example. In} this way, a C-poor layer is formed and during oxidation, little C _I will cluster to form D _it . With the method described herein, for example, the following benefits could be achieved: 1. [V _C ] can be controlled by varying the electron irradiation dose, so to trap C atoms injected during oxidation. 2. Unlike POA or POI, impurities are not incorporated in the oxide. 3. No high annealing temperatures, for example, of about 1300 °C are necessary, as for POA. 4. Unlike N, P or Sb implantation, unwanted impurity-related complexes or other defects are not created. 5. The absence of implanted donor impurities, such as P, close to the surface, prevents normally-on conditions. 6. Reverse engineering is possible in the final product, by monitoring [V _C ] deep in the epilayer, by deep level transient spectroscopy, DLTS, or by photoluminescence, or by performing constant capacitance deep level transient spectroscopy, CC- DLTS. 7. Improved on-state resistance, R _ON , and lower D _it can be achieved. According to at least one embodiment, a kinetic energy of electrons of the low-energy electron radiation is at least 116 keV. Alternatively or additionally, this energy is at most 210 keV. This means, for example, that at least 90% or at least 99% or at least 99.9% of the electrons of the low- energy electron radiation have said kinetic energy. By having such an energy, C atoms of the SiC lattice can specifically be addressed by the radiation to be moved away from the top side. According to at least one embodiment, a dose of the low- energy electron radiation in the first portion is at least ₁₀ ¹⁰ _cm ^-2 _{or is at least 10} ¹² _cm ^-2 _{or is at least 10} ¹⁴ _cm ^-2 _. Alternatively or additionally, it is possible that said dose _{is at most 10} ¹⁷ _cm ^-2 _{or is at most 10} ¹⁶ _cm ^-2 _{or at most 10} ¹⁵ _cm ^-2 _. According to at least one embodiment, the electrical insulation layer contains oxygen. For example, the electrical insulation layer is an oxide layer, in particular a layer of a metal oxide or of a semiconductor oxide. The electrical insulation layer may be of a stoichiometric oxide. According to at least one embodiment, the electrical insulation layer is of SiO ₂ . Otherwise, the electrical ^{insulation layer can be of Al} ₂ ^O ₃ ^{, NO} _x ^{, Y} ₂ ^O ₃ ^{, ZrO} ₂ ^{, HfO} ₂ ^{, La} ₂ ^O ₃ ^{, Ta} ₂ ^O ₅ ^{or TiO} ₂ ^. According to at least one embodiment, the electrical insulation layer is produced by thermal growth. For example, in gas phase the constituents of the electrical insulation layer are provided, which are, for example, Si and O in the case of SiO ₂ . For example, a temperature during producing the electrical insulation layer is at least 600 °C or at least 800 °C or at least 1000 °C. Alternatively or additionally, this temperature is at most 1500 °C or at most 1300 °C or at most 1150 °C. According to at least one embodiment, the producing the electrical insulation layer includes annealing a previously applied material of the electrical insulation layer. It is possible that all or most of the material of the electrical insulation layer has been applied on the top side of the semiconductor body prior to the annealing. For example, a temperature during annealing the electrical insulation layer is at least 200 °C or at least 300 °C or at least 400 °C. Alternatively or additionally, this temperature is at most 1000 °C or at most 800 °C or at most 600 °C. For example, the annealing takes at least 0.5 h or at least 1 h and/or the annealing takes at most 12 h or at most 4 h. It is possible that a temperature during the annealing is lower than during application of the material of the electrical insulation layer. Optionally, during annealing and/or during thermal growth at least one temperature ramp may be applied. According to at least one embodiment, the annealing is done in a nitrogen-containing atmosphere. For example, the annealing is done in an N ₂ atmosphere, which may be free or virtually free of oxygen, or even in air or in one of N ₂ O, NO, O ₂ or O ₃ . The same may apply for the thermal growth of the electrical insulation layer. According to at least one embodiment, the irradiating the at least one first portion is done in a nitrogen-containing atmosphere, which may be free or virtually free of oxygen, or which may be air or also in one of N ₂ O, NO, O ₂ or O ₃ . According to at least one embodiment, the top side of the semiconductor body is a planar surface of the semiconductor body. Hence, the power semiconductor device may be of planar design. According to at least one embodiment, the method further includes the step of forming one or more trenches into the semiconductor body. For example, the at least one trench is formed into the semiconductor body prior to irradiating the at least one first portion. The at least one trench may be produced by etching. Thus, the resulting power semiconductor device could be of a trench design. According to at least one embodiment, the at least one first portion includes side walls and a bottom face of the at least one trench. It is possible that the at least one first region is limited to the side walls and/or to the bottom face of the at least one trench. According to at least one embodiment, the method includes that prior to irradiating the at least one first portion, a mask material is applied on the top side. By means of the mask material, regions of the top side to be irradiated can be defined, or a penetration depth of the low-energy electron radiation into the semiconductor body may be adjusted by means of the mask material or by means of a thickness of the mask material, for a specified material. According to at least one embodiment, during irradiating the at least one first portion the at least one first portion is free of the mask material while remaining portions of the top side are partially or completely covered by the mask material. If the penetration depth of the low-energy electron radiation into the semiconductor body is to be adjusted by means of the mask material in the first portion, too, it is possible that the at least one first portion is partially provided with the mask material, possible with a reduced thickness compared with the other regions of the top side. Even the whole at least one first portion may be covered with a thin layer of the mask material. Using not only one, but a plurality of different mask materials is also possible. According to at least one embodiment, by means of the low- energy electron radiation in the at least one first portion carbon atoms are moved from the top side into the semiconductor body. That is, after irradiating the at least one first portion, the semiconductor body may be of non- stoichiometric SiC. That is, in this area the semiconductor ^{body may have a thin layer of Si} _0.5+x ^C _0.5-x ^{, wherein x may be} at least 0.001 or at least 0.01 and/or x is at most 0.1 or at most 0.02. Said layer may have a thickness of at least 10 nm or of at least 100 nm. Alternatively or additionally, said thickness is at most 1 µm or at most 0.2 µm. A power semiconductor device is additionally provided. The power semiconductor device is produced, for example, by means of the method as indicated in connection with at least one of the above-stated embodiments. Features of the power semiconductor device are therefore also disclosed for the method and vice versa. In at least one embodiment, the power semiconductor device comprises a semiconductor body based on SiC and an electrical insulation layer applied in at least one first portion of a top side of the semiconductor body, wherein next to the electrical insulation layer the semiconductor body is silicon-enriched and, thus, poor of carbon, for example, compared with stoichiometric SiC. According to at least one embodiment, the power semiconductor device is a metal-insulator-semiconductor field-effect transistor, MISFET, or an insulated gate-bipolar transistor, IGBT. According to at least one embodiment, the power semiconductor device is configured for an operating voltage of at least 0.6 kV or of at least 1.2 kV. Alternatively or additionally, the power semiconductor device is configured for an operating voltage of at most 10 kV or of at most 6 kV. According to at least one embodiment, the power semiconductor device is configured for an operating current of at least 10 A or of at least 0.1 kA or of at least 1 kA. Alternatively or additionally, the power semiconductor device is configured for an operating current of at most 20 kA or of at most 5 kA. According to at least one embodiment, the power semiconductor device is a device selected from the following group: a metal–oxide–semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a gate turn-off thyristor (GTO), a gate commutated thyristor (GCT), a junction gate field-effect transistor (JFET). The power semiconductor device is, for example, configured to be used to convert direct current, for example, from a battery to alternating current, for example, for an electric motor. The power semiconductor device may be used, for example, in vehicles like hybrid vehicles or plug-in electric vehicles or also in railways, like commuter trains. A method described herein and a power semiconductor device described herein are explained in greater detail below by way of exemplary embodiments with reference to the drawings. Elements which are the same in the individual figures are indicated with the same reference numerals. The relationships between the elements are not shown to scale, however, but rather individual elements may be shown exaggeratedly large to assist in understanding. Figures 1 to 3 show schematic sectional views of method steps of an exemplary embodiment of a method for producing power semiconductor devices described herein, Figures 4 and 5 show schematic sectional views of method steps of an exemplary embodiment of a method for producing power semiconductor devices described herein, Figure 6 shows a schematic sectional view of a method step of an exemplary embodiment of a method for producing power semiconductor devices described herein, Figure 7 shows a comparison of a voltage vs. capacitance characteristic between an exemplary embodiment of a power semiconductor device described herein and a modified device, Figure 8 shows a comparison of a temperature vs. CC-DLTS characteristic between an exemplary embodiment of a power semiconductor device described herein and a modified device, Figure 9 shows a comparison of a V _GS vs. I _GS characteristic between an exemplary embodiment of a power semiconductor device described herein and a modified device, and Figure 10 shows a comparison of a V _DS vs. I _DS characteristic between an exemplary embodiment of a power semiconductor device described herein and a modified device. In Figures 1 to 3, an example of a method to produce a power semiconductor device 1 is illustrated. According to Figure 1, a semiconductor body 2 is provided. The semiconductor body 2 is based on SiC. For example, the semiconductor body 2 includes a substrate and at least one epitaxially grown semiconductor layer thereon, not shown, wherein both are based on SiC. The semiconductor body 2 has a plane top side 20. For example, the semiconductor body 2 includes a well region 24 which may be of n-type 4H-SiC. Further there can be two p- type regions in the semiconductor body 2. These regions may be a source region 23 and a drain region 5, if the semiconductor body 2 is to be configured as a MOSFET. According to Figure 2, a first portion 21 of the semiconductor body 2 is irradiated with a low-energy electron radiation E. As the top side 20, the first portion 21 is planar. It is possible that the low-energy electron radiation E is limited to the first portion 21 or that more of the top side 20 is exposed to the low-energy electron radiation E. For example, the first portion 21 completely extends between the doped regions 23, 25 and may also include the doped regions 23, 25 partially, seen in top view of the top side 20. Although only one first portion 21 is illustrated in context of Figure 2, there can be a plurality of the first portions 21. Likewise, there can be much more than two of the doped regions 24, 25. For example, a kinetic energy of electrons of the low-energy electron radiation E is at least 116 keV and at most 210 keV. As an option, a dose of the low-energy electron radiation E in the first portion 21 is at least 10 ¹² cm ^-2 and at most ₁₀ ¹⁷ _cm ^-2 _. For example, the irradiating with the radiation E is done in air or a nitrogen atmosphere. Thus, no vacuum may be required in the step of Figure 2. In the method step of Figure 3, an electrical insulation layer 3 is applied to the top side 20 of the semiconductor body 2 in the first portion 21. The electrical insulation layer 3 is produced for example, as a thermal oxide at an elevated temperature of, for example, at least 1000 °C. Optionally, after applying a material of the electrical insulation layer 3, annealing can be performed, for example, in an atmosphere of one of N ₂ O, NO, O ₂ or O ₃ . For example, the electrical insulation layer 3 is of SiO ₂ . By means of the low-energy electron radiation E, carbon atoms are removed from a region next to the top side 20 in the first portion 21 so that in the first portion Si-rich SiC is present. Thus, electrical behavior can be improved as hampering the properly forming the oxide layer of the electrical insulation layer 3 by C clusters is suppressed. Further, in Figure 3 it is shown that on a side of the electrical insulation layer 3 remote from the semiconductor body 3 a gate electrode 4 is formed. The gate electrode 4 may be of a metal or of an ohmically conductive semiconductor material like poly-Si. Depending on the material of the gate electrode 4, the annealing step may be performed after applying a material of the gate electrode 4 so that combined annealing may occur. The finished power semiconductor device 1 is, for example, a power MOSFET or also an IGBT. In case of an IGBT, of course, there is no drain region but there may be a collector region as well as a drift region. Further electrodes beside the gate electrode 4, like a source electrode, a drain electrode or a collector electrode, are not illustrated in the figures. For example, the finished power semiconductor device 1 is configured for currents of at least 10 A and/or of at most 10 kA. Alternatively or additionally, the power semiconductor device 1 is configured for a voltage of at least 0.6 kV and/or of at most 6 kV. In Figures 4 and 5, another example of a manufacturing method is illustrated. According to Figure 4, the semiconductor body 4 is provided, and a trench 5 is formed in the semiconductor body 2. In this case, the finished power semiconductor device 1 will be configured as an IGBT. Thus, the semiconductor body 5 includes a source region 23 at the top side 20. As an option, the source region 23 is divided by the trench 5 in two sub- regions. The source region 23 is embedded in the well region 24. On a side of the well region 24 remote from the top side 20, there is a drift region 26. On a side of the drift region 26 remote from the drift region 26, there is a collector region 25. Again, electrodes for the various semiconductor regions 23, 24, 25 are not illustrate for simplifying the drawing. For example, the trench 5 extends from the top side 20 into the drift region 26 and terminates within the drift region 26. Other than shown, the trench 5 does not need to have a planar bottom face but could have a rounded bottom face or even a V-shaped bottom region, seen in cross-section perpendicular with the top side 20. Moreover, according to Figure 4 at least side walls and the bottom face of the trench 5 are irradiated with the low- energy electron radiation E. That is, the first portion 21 could be composed of said side walls and bottom face. Other parts of the top side 20, outside the trench 5, may also be irradiated with the low-energy electron radiation E. Contrary to what is shown in Figure 4, there can be a plurality of the trenches 5. According to Figure 5, after irradiating the first portion 21 with the radiation E, the electrical insulation layer 3 is applied on the side walls and on the bottom face of the trench 5. In Figure 5, the electrical insulation layer 5 has a constant thickness all along the trench side walls and the bottom face, however, it is also possible that the electrical insulation layer 3 has a varying thickness. Then, the remaining portion of the trench 5 is filled with the gate electrode 4. Otherwise, the same as to Figures 1 to 3 may apply for Figures 4 and 5, and vice versa. In Figure 6, another method to produce the power semiconductor device 1 is illustrated. In this case, a mask material 6 is applied to the top side 20 outside the first portion 21. Thus, second portions 22 outside the first portion 21 may not be irradiated with the low-energy electron radiation E. Accordingly, the first portion 21 can be accurately defined by the mask material 6. A thickness of the mask material 6 can amount to at least 10 µm or to at least 30 µm, for example. Otherwise, the same as to Figures 1 to 5 may apply for Figure 6, and vice versa. Figure 7 shows a comparison of a measured voltage U vs. capacitance C characteristic between an exemplary embodiment of a power semiconductor device 1 described herein and a modified device 9. The modified device 9 corresponds to the power semiconductor device 1 beside the irradiating with the low-energy electron radiation E. Both devices 1, 9 are MOS capacitors. The theoretical flat band voltage, V _FB , is obtained by the difference between the gate metal work function and the semiconductor work function: This results in a value for V _FB of 0.14 eV. From the measured U-C characteristic, a V _FB of 0.38 eV for the pre-irradiated MOS device 1 and 1.80 eV for the reference device 9 can be extracted. Figure 8 shows a comparison of a measured temperature T vs. constant capacitance deep level transient spectroscopy, CC- DLTS, signal S characteristic between the MOS device 1 and the reference device 9. It can be seen that the CC-DLTS signal of the pre-irradiated device 1 is lower than that of the reference device 9, implying a lower D _it . This occurs in the low temperature side of the CC-DLTS spectrum, that is, close to the conduction band edge. To prove the effects of electron irradiation, prior to oxidation, TCAD simulations were carried out on SiC MOSFETs. First, a SiC MOSFET with a typical concentration of interface traps of about 10 ¹² eV ^-1 cm ^-2 was simulated. After that, a SiC MOSFET with the presence of traps that are present after oxidation have been considered, resulting in a one order of magnitude lower: ON1, ON2, OF1, OF2 may be regarded as labels only. Each electrically active level is located in the bandgap. For instance, OF1 is to be found at 0.19 eV below the conduction band edge. Electrically active levels give rise to a potential well, in which electrons fall. This well has a cross section. The larger, the easier to capture electrons. Also, each electrically active level is linked to a defect which, in turn, has a specified concentration. Figure 9 shows a comparison of a V _GS vs. I _GS characteristic between an exemplary embodiment of a power semiconductor device 1 described herein and a modified device 9, and Figure 10 shows a comparison of a V _DS vs. I _DS characteristic between an exemplary embodiment of a power semiconductor device 1 described herein and a modified device 9. Thus Figure 9 refers to transfer characteristics and Figure 10 to output characteristics, with same threshold, of the reference device 9 and pre-oxidation irradiated MOSFET 1 described herein. In Figure 9, simulations performed on a MOSFET, with standard or lower levels, show an improvement of the transfer characteristics if irradiation prior to application of the electrical insulation layer is performed. Figure 10 show the output characteristics of the same MOSFETs. It can be seen that the curve of the irradiated MOSFET 1 shows an improvement with respect to the reference one 9, meaning that the on-resistance, R _ON , has decreased. The components shown in the figures follow, unless indicated otherwise, exemplarily in the specified sequence directly one on top of the other. Components which are not in contact in the figures are exemplarily spaced apart from one another. If lines are drawn parallel to one another, the corresponding surfaces may be oriented in parallel with one another. Likewise, unless indicated otherwise, the positions of the drawn components relative to one another are correctly reproduced in the figures. The power semiconductor device and the method described herein is not restricted by the description on the basis of the exemplary embodiments. Rather, the power semiconductor device and the method encompass any new feature and also any combination of features, which includes in particular any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments. This patent application claims the priority of European patent application 22162 144.4, the disclosure content of which is hereby incorporated by reference.

Reference Signs 1 power semiconductor device 2 semiconductor body 20 top side 21 first portion 22 second portion 23 source region 24 well region 25 drain region 26 drift region 3 electrical insulation layer 4 gate electrode 5 trench 6 mask material 9 modified device C capacitance in pF I _DS current density between drain and source in A/cm2 I _GS current density between gate and source in A/cm2 S CC-DLTS signal in mV T temperature in K U voltage in V V _DS voltage between drain and source in V V _GS voltage between gate and source in V