Title:
MEMORY CELL AND CMOS INVERTER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2020/039996
Kind Code:
A1
Abstract:
A memory cell configured of: a flip flop circuit configured of a first CMOS inverter circuit that comprises a first A transistor TR1 and a first B transistor TR2, and a second inverter circuit that comprises a second A transistor TR3 and a second B transistor TR4; and two transfer transistors TR5, TR6. The first A transistor TR1 and the second A transistor TR2 are connected to a common first power supply line 91, and the first B transistor TR3 and the second B transistor TR4 are connected to a common second power supply line 92.
Inventors:
TOMITA MANABU (JP)
Application Number:
PCT/JP2019/031825
Publication Date:
February 27, 2020
Filing Date:
August 13, 2019
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L21/8244; H01L21/28; H01L21/8229; H01L27/102; H01L27/11; H01L29/417
Domestic Patent References:
| WO2009128450A1 | 2009-10-22 | |||
| WO2009096465A1 | 2009-08-06 |
Foreign References:
| JPH0799311A | 1995-04-11 | |||
| JP2008205168A | 2008-09-04 |
Attorney, Agent or Firm:
YAMAMOTO Takahisa et al. (JP)
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