Title:
MEMORY CONTROLLER AND DATA STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2013/065334
Kind Code:
A1
Abstract:
An estimated cell error rate CERest is set on the basis of an estimated retention time Tret determined from a calculated bit error rate BER, a number of rewrites NW/E, data of a target cell Datatag, and data of a memory cell peripheral to the target cell Dataadj (Step S230); an upper-level page LLRu and a lower-level page LLRl are set for all the bits in a page of data read out using the estimated cell error rate CERest that has been set (Step S250), and the upper-level page LLRu and the lower-level page LLRl set in this manner are used to perform error correction and decoding for data read out from a flash memory (22). This makes it possible to minimize any increase in processing time while enhancing error correction capabilities.
More Like This:
JP2006139631 | RECORDING DEVICE AND COMMUNICATION CONTROL METHOD |
JP2927282 | [Title of Invention] Disk array device |
JPH01263854 | DECIDING SYSTEM FOR MEMORY PARITY ERROR |
Inventors:
TAKEUCHI KEN (JP)
TANAKAMARU SHUHEI (JP)
TANAKAMARU SHUHEI (JP)
Application Number:
PCT/JP2012/058581
Publication Date:
May 10, 2013
Filing Date:
March 30, 2012
Export Citation:
Assignee:
UNIV TOKYO (JP)
TAKEUCHI KEN (JP)
TANAKAMARU SHUHEI (JP)
TAKEUCHI KEN (JP)
TANAKAMARU SHUHEI (JP)
International Classes:
G06F12/16
Foreign References:
JP2011203833A | 2011-10-13 | |||
JP2008108356A | 2008-05-08 | |||
US20100131827A1 | 2010-05-27 | |||
JP2010123236A | 2010-06-03 |
Attorney, Agent or Firm:
ITEC INTERNATIONAL PATENT FIRM (JP)
Patent business corporation Itec international patent firm (JP)
Patent business corporation Itec international patent firm (JP)
Download PDF:
Claims:
Previous Patent: FURNACE, CONTROL DEVICE THEREFOR, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM
Next Patent: PSEUDO-SOLAR RADIATION DEVICE
Next Patent: PSEUDO-SOLAR RADIATION DEVICE