MEMORY DEVICE USING SEMICONDUCTOR ELEMENT

WIPO Patent Application WO/2023/148799

A1

A substrate has formed thereon a first semiconductor layer 1, a part of which has disposed thereon a first impurity layer 3 extending vertically, and a second semiconductor layer 4 is disposed on top of the first impurity layer. The side walls of the impurity layer and the second semiconductor layer, and the semiconductor layer 1 are covered with a first gate insulating layer 2, which has formed therein a groove in which a first gate conductor layer 22 and a second insulating layer 6 are formed. The second semiconductor layer 4 has disposed thereon: a third semiconductor layer 8 which has, on opposite sides thereof, an n+ layer 7a connected to a source line SL and an n+ layer 7b connected to a bit line BL, respectively; a second gate insulating layer 9 formed so as to cover the third semiconductor layer 8; and a second gate conductor layer 10 connected to a word line WL. The work function of the first gate conductor layer 22 at this case exhibits a numeral value higher than that of the second gate conductor layer 10. By controlling the voltages to be applied to the source line SL, a plate line PL that is connected to the first gate conductor layer 22, the word line WL, and the bit line BL, a data retention operation for retaining, in the vicinity of the gate insulating layers, a hole group generated in a channel region of the third semiconductor layer 8 by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erasing operation for removing the hole group from the n layer 3, the n+ layer 7a, and the n+ layer 7b and removing some holes accumulated in a p layer 4 are carried out. It is characterized in that, during the data retention, the hole density of the second semiconductor layer 4 is higher than the hole density of the third semiconductor layer 8.

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KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)

PCT/JP2022/003747

August 10, 2023

February 01, 2022

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UNISANTIS ELECT SINGAPORE PTE (SG)
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)

H01L21/336; H01L27/105; H01L29/788; H01L29/792

US5340754A	1994-08-23
US20200135863A1	2020-04-30
JP2003188279A	2003-07-04
JP2008147514A	2008-06-26

TANAKA Shinichiro et al. (JP)

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