A METHOD AND APPARATUS FOR ERROR CONTROLLING IN HIGH SPEED WIRELESS PACKET DATA SERVICE

WIPO Patent Application WO/2003/071739

A1

This invention discloses a method for error controlling in high speed wireless packet data service, wherein: adopts double channel control for transmitted packet data, implements the error controlling of the transmitted packet data by setting waiting flag bit and setting the transmitted packet counter. This invention discloses an apparatus for error controlling in high speed wireless packet data service, wherein: by setting waiting flag bit and transmitted packet counter for parity channel in double channel controller, implements DSW ARQ parity channel scheduling, implements error controlling for transmitted packet. By use of the method of this invention it advances the utilization rate of channels, thus advances the validity of the whole communication system; at the same time, it facilitates dispatch and fault diagnosis and scales down the systemic complexity congratulation and time lag.

JP4157043	Receiver of wireless communication system using at least 3 transmitting antennas
WO/2020/144828	TRANSMISSION DEVICE, RECEPTION DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD
WO/2009/087329	TIME-RETURN PRE-EQUALISATION METHOD

WU CHENGMING (CN)
LIU XIAOHUA (CN)
WU XIAOBIN (CN)

PCT/CN2002/000106

August 28, 2003

February 21, 2002

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LINKAIR COMM INC (US)
WU CHENGMING (CN)
LIU XIAOHUA (CN)
WU XIAOBIN (CN)

H04L1/06; H04L1/18; H04L12/28; H04L1/16; (IPC1-7): H04L12/28

CN1313013A	2001-09-12
US6301249B1	2001-10-09
US6148422A	2000-11-14

BEIJING SANYOU INTELLECTUAL PROPERTY AGENT LTD. (No.40 North Sanhuanzhonglu Road Beijing 8, CN)

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