CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is related to and claims the priority of U.S. Provisional Patent Application No. 62/979,059, filed February 20, 2020, the entirety of which is hereby incorporated herein by reference.

BACKGROUND

[0002] Embodiments of the present disclosure relate to apparatuses and methods for packet de-segmentation and reassembly, which may be applicable to communication systems, such as wireless communication systems. [0003] In communication systems, such as wireless communication systems (e.g., fourth-generation (4G) or fifth -generation (5G)), medium access control (MAC) layer data packets may be larger than the physical (PHY) layer can accommodate. Accordingly, the MAC layer data packets may be broken up into pieces at the transmitter side and reassembled at the receiver side. The receiver side processing is typically accomplished by using software to assemble segments into a complete service data unit (SDU).

SUMMARY

[0004] Embodiments of apparatuses and methods for de-segmentation are disclosed herein. The apparatuses may be variously implemented as user equipment, systems-on-chip, or the components or sub-components, such as the physical layer thereof.

[0005] For example, a baseband chip can include at least one memory configured to store at least a descriptor of a first packet segment having a first segment offset value. The baseband chip can also include a de segmentation circuit configured to compare a second segment offset value of a second packet segment to the first segment offset value. The de-segmentation circuit can be configured to store a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value.

[0006] As an additional example, a baseband chip can include at least one memory configured to store at least a descriptor of a first packet segment having a first segment offset value. The baseband chip can also include at least one processor configured to compare a second segment offset value of a second packet segment to the first segment offset value. The at least one processor can be configured to store a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value.

[0007] As another example, a method for de-segmentation can include storing at least a descriptor of a first packet segment having a first segment offset value in at least one memory. The method can also include comparing, by a de-segmentation circuit, a second segment offset value of a second packet segment to the first segment offset value. The method can further include storing, by the de-segmentation circuit, a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value. [0008] As a further example, a non-transitory computer-readable medium can be encoded with instructions that, when executed in hardware, perform a process. The process can include storing at least a descriptor of a first packet segment having a first segment offset value in at least one memory. The process can further include comparing a second segment offset value of a second packet segment to the first segment offset value. The process can additionally include storing a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value.

[0009] As another example, an apparatus for de-segmentation can include means for storing at least a descriptor of a first packet segment having a first segment offset value. The apparatus can further include means for comparing a second segment offset value of a second packet segment to the first segment offset value. The apparatus can additionally include means for storing a descriptor of the second packet segment in the means for storing in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0011] FIG. 1A illustrates a long term evolution (LTE) radio link control (RLC) header format with 10 bit sequence number (SN) and 15 bit segment offset (SO), according to certain embodiments of the present disclosure.

[0012] FIG. IB illustrates an LTE RLC header format with 16 bit SN and 16 bit segment offset SO, according to certain embodiments of the present disclosure.

[0013] FIG. 2 illustrates an example of a possible incoming packet flow with out of order segments for a given SN of an RLC protocol data unit (PDU) flow, according to certain embodiments of the present disclosure. [0014] FIG. 3 A illustrates a descriptor format for an RLC segment having a 10-bit SN, according to certain embodiments of the present disclosure.

[0015] FIG. 3B illustrates a descriptor format for an RLC segment having a 16-bit SN, according to certain embodiments of the present disclosure.

[0016] FIG. 4 illustrates a de-segmentation linear memory, according to certain embodiments of the present disclosure.

[0017] FIG. 5 A illustrates a method for de-segmentation, according to certain embodiments of the present disclosure.

[0018] FIG. 5B illustrates a detailed block diagram of an example baseband chip implementing Layer 2 downlink data processing, such as de-segmentation, according to some embodiments of the present disclosure. [0019] FIGs. 6A, 6B, 6C, 6D, 6E, 6F, and 6G illustrate various stages of a sorting approach, according to certain embodiments of the present disclosure.

[0020] FIG. 7A illustrates an example of a hardware function for de-segmentation checking, according to certain embodiments.

[0021] FIG. 7B illustrates another example of a hardware function for de-segmentation checking, according to certain embodiments.

[0022] FIG. 8 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency chip, and a host chip, according to certain embodiments of the present disclosure.

[0023] FIG. 9 illustrates an exemplary wireless network that may incorporate packet de-segmentation, in which some aspects of the present disclosure may be implemented, according to certain embodiments of the present disclosure.

[0024] FIG. 10 illustrates a node that may implement packet de-segmentation, according to certain embodiments of the present disclosure.

DETAILED DESCRIPTION

[0025] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0026] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0027] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. [0028] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0029] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC-FDMA) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT) such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT such as GSM. An OFDMA network may implement a RAT, such as long term evolution (LTE) or new radio (NR). The techniques and system described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs. Likewise, the techniques and systems described herein may also be applied to wired networks, such as networks based on optical fibers, coaxial cables, or twisted-pairs, or to satellite networks.

[0030] When high data throughput and packet rates are required, software reassembly of SDUs may require a significant amount of central processing unit (CPU) resources to compute. Additionally, this process may cause excessive power consumption.

[0031] For example, software may be used to locate segments to be assembled in the packet buffer. Since the sequence number (SN) can be 18 bits, the software may have to search through 2 ^L 17 memory locations to find the segments. This may be a very slow and power-consuming process.

[0032] Certain embodiments of the present disclosure include a hardware-based method and process that may effectively reassemble multiple radio link control (RLC) protocol data unit (PDU) segments into a whole RLC SDU.

[0033] Certain embodiments may have various benefits or advantages relative to a software-based approach including, but not limited to, a reduction of power consumption, reduction of data buffers, improved speed, and fewer processing delays.

[0034] Certain embodiments may be used in high performance, low cost, low power 4G/5G modem MAC layer design. The 4G/5G standard systems are used as examples, as certain embodiments may also be applicable to other communication standards. For example, any communication system where reassembly of packets at a higher layer of the protocol stack is required because of limitations of a lower level of the protocol stack may benefit from certain embodiments of the present disclosure.

[0035] In the Third-Generation Partnership Project (3GPP), for example, in Long Term Evolution (LTE), one acknowledged mode data (AMD) RLC SDU, which can be a packet from the packet data convergence protocol (PDCP) layer, can be segmented into multiple segments or pieces. 3GPP has defined RLC header information to identify each AMD segment. FIGs. 1A and IB are two examples of the header formats for LTE. Other formats are equally applicable, such as the format for 5G new radio (NR). Certain embodiments are equally applicable to 5G NR design.

[0036] FIG. 1A illustrates an LTE RLC header format with 10 bit sequence number (SN) and 15 bit segment offset (SO). FIG. IB illustrates an LTE RLC header format with 16 bit SN and 16 bit segment offset SO. As mentioned above, other formats are also permitted, with these simply being provided as two illustrative and non limiting examples.

[0037] As shown in FIGs. 1A and IB, there can be a one-bit indication of data or control (D/C), a re segmentation flag (RF), a one-bit polling request flag (P), two bits of framing indication (FI), a one-bit header format expansion enablement flag (E), and a one-bit last segment flag (LSF). In FIG. IB, there is also a one-bit reserved field (Rl).

[0038] In FIGs. 1A and IB, the SO can be a 15 bit or 16 bit number that indicates the first byte position of the segment relative to the beginning of the original RLC SDU. Thus, the SO of the first RLC segment is all zeros: SO = 0. FIGs. 1A and IB are diagrams of 4G LTE. For 5G NR, the diagrams are very similar. The same segmentation parameters are likewise defined for 5G NR, namely SN and SO. Some of the differences between LTE and NR will be discussed below.

[0039] Due to re-transmission and other receive processes, at DL, the receiving end of 4G/5G link, segments of an RLC SDU could be received in any order. Thus, the receive side cannot safely assume any particular order of incoming segments of an RLC SDU. FIG. 2 illustrates an example of a possible incoming packet flow with out of order segments for a given SN of an RLC PDU flow.

[0040] As shown in FIG. 2, segment SO_2 could arrive before segment SO_l. Likewise, segment SO_4 could arrive after segment SO_6, for example, and so on. Finding the right segment at the right position may be done in one option, by relying on the segment offset value. Because the segment offset may be a 16-bit value, there could be a large search range for segments. Certain embodiments avoid the need for such searching. For example, certain embodiments employ a segment order sorting mechanism, using a streaming hardware architecture to avoid the need for a large search range and associated software implementation.

[0041] In certain embodiments of the present disclosure, as illustrated in FIG. 2, data can come in from MAC in a streaming interface in which packets are sent to RLC one after another without assuming any sequence order. The packet or segments could be completely out of order.

[0042] In certain aspects of a hardware approach, each data packet can be stored in a buffer allocated by a buffer manager. A descriptor of each packet can be created by the MAC layer and sent to the RLC de segmentation module. The de-segmentation module can be a part of the reassembly process that ultimately results in reassembled packets emerging from the protocol stack. The descriptor can include information including the sequence number (SN), segment offset (SO), segment length of the packet payload in bytes, and any other related information for RLC processing. FIGs. 3A and 3B illustrate examples of descriptors that could be used.

[0043] FIG. 3 A illustrates a descriptor format for an RLC segment having a 10-bit SN, according to certain embodiments of the present disclosure. FIG. 3B illustrates a descriptor format for an RLC segment having a 16- bit SN, according to certain embodiments of the present disclosure. As shown in FIG. 3B, the SN and SO may span two octets, and accordingly, the first bits of each may be in a first octet, and the remaining bits may be a second octet. For example, bits 15 through 8 may be in a first octet, while bits 7 through 0 may be in a second octet. Other arrangements of bits are also permitted.

[0044] Based on the 3GPP LTE standard, the RLC PDU sessions may be configured such that each PDU stream has the same RLC PDU header format, which can be one of the two formats illustrated in FIGs. 1A and IB. Thus, either the 10 bit or 16 bit descriptor may be applicable in such circumstances. NR may have similar requirements and may use the same approach.

[0045] If a 24-bit sequence number were to be used, for example, more bits in the descriptor could be allocated to the sequence number. Other implementations are also possible.

[0046] The hardware of certain embodiments may use a reassembly memory to store the above-described descriptors. The descriptors may be stored in a linear memory space in which each entry is 8 bytes, the size of the descriptors in FIGs. 3 A and 3B.

[0047] FIG. 4 illustrates a de-segmentation linear memory according to certain embodiments of the present disclosure. In FIG. 4, all of the segments are shown stored in memory in sequence order. In the best-case scenario, all of the segments would be received and stored in order. In which case, no rearrangement of the segments would be necessary. In a more typical case, some of the segments may arrive out of order, and consequently, rearrangement of the segments may be necessary in order to achieve a sequentially ordered memory.

[0048] FIG. 5A illustrates a method for de-segmentation according to certain embodiments. As shown in FIG. 5A, a method 550 can include, at 552, receiving a packet with an indication of SO. If the packet, for example, an RLC segment PDU, arrives out of order as shown in FIG. 2, the hardware of a system implementing certain embodiments (see, for example, apparatus 500 in FIG. 5B) may, at 554, compare the SO of the packet with the last segment in the de-segmentation memory to see which SO is bigger. If the current segment has a bigger SO, then at 556, the current segment descriptor may be stored at the end of the memory space. If the current segment’s SO is smaller than the last segment in memory, they will swap positions. The comparison of SO can serve to identify which segment is prior to the other segment in terms of sequence order. A smaller SO implies that the segment having such an SO is prior to a segment having a larger SO. This priority may simply be a priority in original position within the packet, not a priority of value, time, or anything else. Indeed, it is possible that the segments may be received out of order because they may be transmitted out of order. Likewise, while a segment with a smaller SO may be prior to a segment with a larger SO, the segment with the larger SO may have a greater significance or value.

[0049] Swapping positions can be accomplished by moving the last segment’s descriptor down in memory at 558, and then potentially saving the current segment’s descriptor at the place where the last segment’s descriptor had been saved. Moving down the descriptor can be performed various ways. For example, a copy of the descriptor can be written immediately following the original of the descriptor in contiguous memory. Then the original of the descriptor can be dereferenced, erased, overwritten, or otherwise treated as available. Before saving the current segment’s descriptor to the newly opened space, the system implementing method 550 can, at 560, compare the current segment’s SO to that of the next previous segment’s descriptor in memory. If the current segment’s SO is larger, then at 562, the current segment’s descriptor can be saved at the current position. Otherwise, the next previous segment can be moved down at 564, and the comparison and swapping can continue until either the current segment’s SO becomes smaller than a previous segment’s SO or the top of the list is reached. If the top of the list and there is no smaller SO, the current segment’s descriptor can be stored at the top of the list.

[0050] FIG. 5B illustrates a detailed block diagram of an example baseband chip 502 implementing Layer 2 downlink data processing using Layer 2 circuits 508 and an MCU 510, according to some embodiments of the present disclosure. The baseband chip 502 or components thereof may implement the method shown in FIG. 5A. In some embodiments, as shown in FIG. 5B, layer 2 circuits 508 include an SDAP circuit 520, a PDCP circuit 522, an RLC circuit 524, and a MAC circuit 526. The approach of FIG. 5B may rely on integrated circuits (ICs) (e.g., SDAP circuit 520, PDCP circuit 522, RLC circuit 524, and MAC circuit 526) to conduct Layer 2 downlink data processing. In some embodiments, each of SDAP, PDCP, RLC, and MAC circuits 520, 522, 524, or 526 is an IC dedicated to performing the functions of the respective layer in Layer 2 user plane. For example, each of SDAP, PDCP, RLC, and MAC circuits 520, 522, 524, or 526 may be an ASIC, which is customized for a particular use, rather than intended for general-purpose use, and thus, is known for its high speed, small die size, and low power consumption compared with a generic processor.

[0051] Apparatus 500 may be any suitable node of wireless network 900 in FIG. 9, such as user equipment 902 or access node 904 (e.g., a base station including eNB in LTE or gNB in NR). As shown in FIG. 5B, apparatus 500 may include baseband chip 502, a host chip 504, an external memory 506, and a main bus 538 (also known as a “system bus”) operatively coupling baseband chip 502, host chip 504, and external memory 506. That is, baseband chip 502, host chip 504, and external memory 506 may exchange data through main bus 538. External memory 506 can be shared by host chip 504, baseband chip 502, or any other suitable components in apparatus 500, such as a system memory (also known as a “main memory” or “primary memory”) of apparatus 500. [0052] As shown in FIG. 5B, baseband chip 502 may also include a plurality of direct memory access (DMA) channels including a first DMA channel (DMA CHI) 516 and a second DMA channel (DMA CH2) 518. Each DMA channel 516 or 518 can allow certain Layer 2 circuits 508 to access external memory 506 directly independent of host chip 504. In some embodiments, DMA channels 516 and 518 may include a DMA controller and any other suitable input/output (I/O) circuits. As shown in FIG. 5B, baseband chip 502 may further include a local memory 514, such as an on-chip memory on baseband chip 502, which is distinguished from external memory 506 that is an off-chip memory not on baseband chip 502. In some embodiments, local memory 514 includes one or more LI, L2, L3, or L4 caches. Layer 2 circuits 508 may access local memory 514 through main bus 538 as well. The local memory 514 may be used to store and sort the packet descriptors discussed above and illustrated in a sorted form in FIG. 4.

[0053] As shown in FIG. 5B, baseband chip 502 may further include a memory 512 that can be shared by (e.g., both accessed by) Layer 2 circuits 508 and MCU 510. Although memory 512 is shown as an individual memory separate from local memory 514, in some examples, memory 512 and local memory 514 may be local partitions of the same physical memory structure, for example, an SRAM. In one example, a logical partition in local memory 514 may be dedicated to or dynamically allocated to Layer 2 circuits 508 and MCU 510 for exchanging control commands and result statuses when baseband chip 502 is in the interactive mode. In some embodiments, memory 512 includes a plurality of command queues 534 for storing a plurality sets of commands, respectively, and a plurality of status queues 536 for storing a plurality sets of result statuses, respectively. Each pair of corresponding command queue 534 and status queue 536 may be dedicated to one of Layer 2 circuits 508. [0054] As shown in FIG. 5B, baseband chip 502 may further include a local bus 540. In some embodiments, MCU 510 is operatively coupled to memory 512 and main bus 538 through local bus 540. Referring to Layer 2 circuits 508, Layer 2 circuits 508 may be configured to receive Layer 1 transport blocks (as the inputs of Layer 2 circuits 508) and generate Layer 3 data packets (as the outputs of Layer 2 circuits 508) from the Layer 1 transport blocks in an inline manner. In some embodiments, Layer 2 circuits 508 are configured to pass data through each layer of Layer 2 circuits 508 without storing the data in external memory 506. The data may flow from lower to upper layers in Layer 2 (e.g., MAC circuit 526, RLC circuit 524, and PDCP circuit 522).

[0055] As shown in FIG. 5B, MCU 510 may be operatively coupled to Layer 2 circuits 508 and configured to control Layer 2 circuits 508 to generate Layer 3 data packets from the Layer 1 transport blocks through a plurality sets of commands. In some embodiments, besides SDAP circuit 520, PDCP circuit 522, RLC circuit 524, and MAC circuit 526, each of which corresponds to one layer in Layer 2 user plane in LTE or NR, Layer 2 circuits 508 includes additional hardware components including a flow control buffer 528, a MAC-PHY interface 530, and a buffer management (BM) circuit 532.

[0056] As shown in FIG. 5B, MAC-PHY interface 530 may be operatively coupled to flow control buffer 528 and configured to receive the Layer 1 transport blocks from Layer 1 (e.g., the PHY layer). The operations of MAC-PHY interface 530 may be controlled based on a set of interface commands from MCU 510. In some embodiments, each Layer 1 transport block is divided into a plurality of code blocks (CBs), and MAC-PHY interface 530 receives the Layer 1 transport blocks in the unit of each code block through code block -related signals, such as CB DATA indicative of the data values of a code block, CB START indicative of the start of a new code block, CB LENGHT indicative of the length of the code block, and CB INDEX indicative of the order number of the code block in the received transport block.

[0057] As shown in FIG. 5B, flow control buffer 528 may be operatively coupled to MAC-PHY interface 530 and configured store the Layer 1 transport blocks received by MAC-PHY interface 530. Flow control buffer 528 may be a separate physical memory component or part of local memory 514 (e.g., a logical partition thereof) dedicated to Layer 2 downlink data processing. In some embodiments, flow control buffer 528 can be further configured to buffer the Layer 1 transport blocks to be adapted to Layer 1 data rate, for example, when the Layer 1 data rate exceeds the peak Layer 2 downlink data processing capability of baseband chip 502. Layer 2 circuits 508 in baseband chip 502 can perform Layer 2 downlink data processing in an inline manner without access to external memory 506. In order to adapt to the higher Layer 1 data rate, flow control buffer 528 may perform the MAC-PHY flow control function by buffering the Layer 1 transport blocks. It is understood that in some examples, second DMA channel 518 operatively coupled to flow control buffer 528 and MAC-PHY interface 530 may be configured to transmit some of the Layer 1 transport blocks from flow control buffer 528 or directly through MAC-PHY interface 530 to external memory 506 to overflow the Layer 1 transport blocks when the capacity of flow control buffer 528 is overloaded, for example, by an extremely high Layer 1 data rate.

[0058] Besides Layer 1 data rate adaptation, flow control buffer 528 can be used for code block re-organization as well when the received code blocks are not in order. Moreover, as described below in detail, the payload and headers of each Layer 1 transport block can be processed separately to reduce the workload and power consumption of baseband chip 502. In some embodiments, the payload of a Layer 1 transport block is stored in flow control buffer 528 until the headers of the Layer 1 transport block have been processed by Layer 2 circuits 508 (e.g., MAC circuit 526, RLC circuit 524, and/or PDCP circuit 522).

[0059] As shown in FIG. 5B, MAC circuit 526 may be operatively coupled to flow control buffer 528 and RLC circuit 524 and configured to process the MAC headers of the Layer 1 transport blocks stored in flow control buffer 528. The processing of the MAC headers by MAC circuit 526 may be controlled based on a set of MAC commands from MCU 510. In some embodiment, MCU 510 is configured to retrieve/read the set of interface result statuses (i.e., the result statues from MAC-PHY interface 530) from interface status queue 536, generate the set of MAC commands based on the set of interface result statuses, and store/write the set of MAC commands into a MAC command queue 534 in memory 512, such that MAC circuit 526 can retrieve/read the set of MAC commands from MAC command queue 534 according to the priorities assigned by MCU 510 to the MAC commands. For example, the MAC commands may need to be adjusted based on the processing result at MAC- PHY interface 530, e.g., wait until all the code blocks of the next Layer 1 transport block have been received and organized in order in flow control buffer 528. In some embodiments, MAC circuit 526 is configured to process only the MAC header, but not the payload of a Layer 1 transport block stored in flow control buffer 528. For example, MAC circuit 526 may extract the MAC header from the Layer 1 transport block and read only the MAC header, but not the payload, of the Layer 1 transport block. It is understood that in some examples, MAC circuit 526 may extract and read other headers of the Layer 1 transport block as well, such as RLC header and PDCP header. Nevertheless, MAC circuit 526 does not read the payload of the Layer 1 transport block, and does not process other headers, such as RLC header and PDCP headers, according to some embodiments.

[0060] The flow control buffer 528 may be an example of a memory that can be used to store the packet segment descriptors discussed above. The organization of the packet descriptors in the flow control buffer 528 may be performed by circuitry, such as RLC circuit 524 or another processor or circuit, including an application-specific integrated circuit.

[0061] As shown in FIG. 5B, RLC circuit 524 may be operatively coupled to MAC circuit 526 and PDCP circuit 522 and configured to process the RLC headers of the Layer 1 transport blocks received from MAC circuit 526. The processing of the RLC headers may be controlled based on a set of RLC commands from MCU 510. As mentioned above, the RLC circuit 524 may be configured to reorganize the packet segments received at the MAC layer. As another alternative, the reorganizing leading to de-segmentation may be assisted by the MAC circuit 526 or another circuit or processor.

[0062] The RLC layer in uplink, implemented by RLC circuit 524, may be involved in segmenting or concatenating the data packets received from the upper layer, e.g., the PDCP PDUs/RLC SDUs, into each RLC PDU. That is, the RLC circuit 524 may pack small data packets together to form a large data packet (e.g., in LTE) or break down a large data packet into multiple smaller data packets. Depending on the mode of operations (e.g., the transparent mode (TM), the unacknowledged mode (UM), or the acknowledged mode (AM)), the RLC circuit 524 may further perform error correction through automatic repeat request (ARQ) in the AM mode, reassembly of RLC SDUs in the UM and AM modes, duplication detection in the UM and AM modes, and RLC SDU discard in the UM and AM modes. In some embodiments, the RLC circuit 524 can perform RLC re transmission by inserting re-transmitted data packets.

[0063] In some embodiments, the functions of RLC circuit 524 in processing the RLC headers are defined by the 3GPP standards with respect to the RLC layer. For example, RLC circuit 524 may perform segmentation, reassembly (also known as de-segmentation), duplication detection, and/or in-order delivery in three modes by processing the RLC headers of the Layer 1 transport blocks, which are extracted and read from flow control buffer 528. It is understood that in case any update or change being made to the required functions of the RLC Layer, MCU 510 may reflect the update or change in its RLC commands to control RLC circuit 524 to act accordingly. As shown in FIG. 5B, RLC circuit 524 may be further configured to obtain the processing result, for example, once the RLC Layer processing is completed, halted, or interrupted, and store a set of result statuses indicative of the processing result into an RLC status queue 536 in memory 512.

[0064] As shown in FIG. 5B, PDCP circuit 522 may be operatively coupled to RLC circuit 524 and SDAP circuit 520 and configured to process the PDCP headers of the Layer 1 transport blocks received from RLC circuit 524. The processing of the PDCP headers may be controlled based on a set of PDCP commands from MCU 510.

[0065] The practice of the approach of FIG. 5A, which may be implemented by the apparatus 500 of FIG. 5B can be seen through the following examples, which are merely illustrative of the principles. FIGs. 6A, 6B, 6C, 6D, 6E, 6F, and 6G illustrate various stages of a sorting approach according to certain embodiments of the present disclosure.

[0066] Referring to FIG. 6A, when SO O came, there was nothing yet in the de-segmentation memory (also referred to as a de-segmentation queue). Thus, SO O was stored at the beginning of the memory. When SO_2 came, the SO of SO_2 was bigger than SO O, so it was stored at the end of the memory. At this time, as shown FIG. 6A, the out of order SO_l comes in. Thus, the hardware can compare the SO of SO_l with that of SO_2. Because SO_l has a smaller SO, as shown in FIG. 6B, the hardware can relocate SO_2 to the end of the memory and place SO_l in front of SO_2.

[0067] The hardware can repeat these kinds of comparison and movement operations until the current segment RLC PDU is at the right de-segmentation memory location, where the current segment’s SO is smaller than the segment before it, and the current segment’s SO is bigger than the segment after it. The next RLC PDU segment could do the same in the hardware. For example, as shown in FIG. 6C, SO_3 can come in next. Thus, the hardware can compare the SO of SO_3 to the SO of the last segment descriptor in memory, which is SO_2. In this case, because the SO of SO_3 is greater than the SO of SO_2, as shown in FIG. 6D, SO_3 can be stored in the first empty slot, and the next empty slot can be the empty slot for the next incoming segment.

[0068] When the last segment descriptor in memory has a smaller SO than a continuous group of incoming segments, such as segments SO_5 and SO_6 in FIG. 6E, the hardware could alternatively move the entire group together. This may reduce memory access time, but may require an additional check to identify whether the incoming segments are sequential.

[0069] Similarly, as one option, the hardware may keep track of consecutive segments and minimize the number of comparisons to the last segment in a consecutive set.

[0070] For example, as shown FIG. 6F, out of order segment SO_4 may arrive after consecutive segments SO_5 and SO_6. As shown in FIG. 6F, the SO of SO_4 may be compared sequentially to each of segments SO_6, SO_5, and SO_3. Upon the comparison to SO_3, as shown FIG. 6G, segment SO_4 can be inserted after SO_3, and SO_5 and SO_6 can be individually or collectively moved into lower slots such that ultimately the next empty slot becomes the new empty slot. Ultimately, once all the segments have been received, the de segmentation queue may look as shown in FIG. 4.

[0071] If there are any segments that have a duplicate SO, the sorting algorithm may discard the duplicated segment. The hardware may assume duplication of the SO of the received packet is equal to the SO of a compared packet descriptor in the memory.

[0072] De-segmentation completion checking and reconciliation can be performed by a separate hardware function after the last segment is received. FIG. 7A illustrates an example of a hardware function for de segmentation checking according to certain embodiments. The hardware function may check and validate if de segmentation is fully finished. One option is that the hardware function can start from the first segment and calculate the SO of the next segment using the following formula: SO next = SO current + Current Packet Payload Length.

[0073] SO next can refer to the SO of the next segment to be read. SO current can refer to the SO of the segment that is currently being examined. If this condition is valid for all segments from the first segment to the last segment, the de-segmentation can be declared to be completed. If at any point, this condition is not valid, then the de-segmentation can be declared un-finished and incomplete. The hardware function, which may be an integrated circuit such as an application-specific integrated circuit (ASIC), can do this check for every segment that is received after receiving the last segment of the same SN until de-segmentation complete is declared or a de-segmentation time out occurs.

[0074] Once de-segmenting is declared complete, the hardware can set an interrupt to a software module (or a further hardware module) and pass the descriptor list to the software module (or further hardware module) for further processing of the fully reassembled RLC SDU.

[0075] Another option is to start from the last segment. FIG. 7B illustrates another example of a hardware function for de-segmentation checking according to certain embodiments. FIG. 7B is like FIG. 7A, except that the hardware function may be checking up the memory instead of down the memory. This option may have the advantage or benefit of allowing the checking to be done at the same time with the sorting processes so that no extra processing time is required. The equation in such a situation may be as follows: SO current = SO_previous - Current Packet Payload Length.

[0076] Any memory can be used as de-segmentation memory. On-chip static random access memory (SRAM) would be an example of relatively fast hardware that could be used. As an example, using on-chip SRAM, the hardware could use one cycle for one memory read and compare two more cycles to finish swapping two memory locations. Thus, in total, hardware can use three clock cycles to sort every segment received. In the worst case, assuming there are N segments in the de-segmentation memory, to swap all N segment locations in the de segmentation memory, the hardware would use 3N cycles following this example approach. For the de segmentation checking and reconciliation, if de -segmentation starts from the last segment, no extra cycles may be required. Thus, the overall hardware worst-case clock cycle count is 3N for RLC SDUs with N segments. [0077] The delay may be longer when there are more segments. In practice, if there are not more than two or three segments per RLC SDU, total hardware cycles may be less than 10 clock cycles for each segment received. This is okay because the de-segmentation process usually is branched offline and not in the timing critical path of hardware process.

[0078] Certain embodiments may have various benefits and/or advantages. For example, certain embodiments may have lower power consumption due to efficient hardware operations, which may be very important for mobile communication devices. Additionally, certain embodiments may have improved data processing speed due to the fast hardware process compared to slower software processes. The software and hardware methods and systems disclosed herein, such as method 550 in FIG. 5 A, may be implemented by any suitable nodes in a wireless network. For example, FIG. 8 illustrates an apparatus 800, and FIG. 9 illustrates an exemplary wireless network 900, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0079] FIG. 8 illustrates a block diagram of an apparatus 800 including a baseband chip 802, a radio frequency chip 804, and a host chip 806, according to some embodiments of the present disclosure. Apparatus 800 may be an example of any suitable node of wireless network 900 in FIG. 9, such as user equipment 902 or access node 904. As shown in FIG. 8, apparatus 800 may include baseband chip 802, radio frequency chip 804, host chip 806, and one or more antennas 810. In some embodiments, baseband chip 802 is implemented by processor 1002 and memory 1004, and radio frequency chip 804 is implemented by processor 1002, memory 1004, and transceiver 1006, as described below with respect to FIG. 10. Besides the on-chip memory (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 802, 804, or 806, apparatus 800 may further include an external memory 808 (e.g., the system memory or main memory) that can be shared by each chip 802, 804, or 806 through the system/main bus. Although baseband chip 802 is illustrated as a standalone SoC in FIG. 8, it is understood that in one example, baseband chip 802 and radio frequency chip 804 may be integrated as one SoC; in another example, baseband chip 802 and host chip 806 may be integrated as one SoC; in still another example, baseband chip 802, radio frequency chip 804, and host chip 806 may be integrated as one SoC, as described above.

[0080] In the uplink, host chip 806 may generate raw data and send it to baseband chip 802 for encoding, modulation, and mapping. Baseband chip 802 may also access the raw data generated by host chip 806 and stored in external memory 808, for example, using the direct memory access (DMA). Baseband chip 802 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi - phase pre-shared key (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 802 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 802 may send the modulated signal to radio frequency chip 804. Radio frequency chip 804, through the transmitter (Tx), may convert the modulated signal in the digital form into analog signals, i.e., radio frequency signals, and perform any suitable front-end radio frequency functions, such as filtering, up- conversion, or sample-rate conversion. Antenna 810 (e.g., an antenna array) may transmit the radio frequency signals provided by the transmitter of radio frequency chip 804. [0081] In the downlink, antenna 810 may receive radio frequency signals and pass the radio frequency signals to the receiver (Rx) of radio frequency chip 804. Radio frequency chip 804 may perform any suitable front-end radio frequency functions, such as filtering, down-conversion, or sample-rate conversion, and convert the radio frequency signals into low-frequency digital signals (baseband signals) that can be processed by baseband chip 802. In the downlink, baseband chip 802 may demodulate and decode the baseband signals to extract raw data that can be processed by host chip 806. Baseband chip 802 may perform additional functions, such as error checking, de-mapping, channel estimation, descrambling, etc. The raw data provided by baseband chip 802 may be sent to host chip 806 directly or stored in external memory 808.

[0082] As shown in FIG. 9, wireless network 900 may include a network of nodes, such as a UE 902, an access node 904, and a core network element 906. User equipment 902 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (IoT) node. It is understood that user equipment 902 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0083] Access node 904 may be a device that communicates with user equipment 902, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 904 may have a wired connection to user equipment 902, a wireless connection to user equipment 902, or any combination thereof. Access node 904 may be connected to user equipment 902 by multiple connections, and user equipment 902 may be connected to other access nodes in addition to access node 904. Access node 904 may also be connected to other UEs. It is understood that access node 904 is illustrated by a radio tower by way of illustration and not by way of limitation. [0084] Core network element 906 may serve access node 904 and user equipment 902 to provide core network services. Examples of core network element 906 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 906 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It is understood that core network element 906 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0085] Core network element 906 may connect with a large network, such as the Internet 908, or another IP network, to communicate packet data over any distance. In this way, data from user equipment 902 may be communicated to other UEs connected to other access points, including, for example, a computer 910 connected to Internet 908, for example, using a wired connection or a wireless connection, or to a tablet 912 wirelessly connected to Internet 908 via a router 914. Thus, computer 910 and tablet 912 provide additional examples of possible UEs, and router 914 provides an example of another possible access node.

[0086] A generic example of a rack-mounted server is provided as an illustration of core network element 906. However, there may be multiple elements in the core network including database servers, such as a database 916, and security and authentication servers, such as an authentication server 918. Database 916 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 918 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 906, authentication server 918, and database 916, may be local connections within a single rack.

[0087] Although the above-description used uplink and downlink processing of a packet in a UE as examples in various discussions, similar techniques may likewise be used for the other direction of processing and for processing in other devices, such as access nodes, and core network nodes. For example, any device that processes packets through a plurality of layers of a protocol stack may benefit some embodiments of the present disclosure, even if not specifically listed above or illustrated in the example network of FIG. 9.

[0088] Each of the elements of FIG. 9 may be considered a node of wireless network 900. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 1000 in FIG. 10 below. Node 1000 may be configured as user equipment 902, access node 904, or core network element 906 in FIG. 9. Similarly, node 1000 may also be configured as computer 910, router 914, tablet 912, database 916, or authentication server 918 in FIG. 9.

[0089] As shown in FIG. 10, node 1000 may include a processor 1002, a memory 1004, a transceiver 1006. These components are shown as connected to one another by bus 708, but other connection types are also permitted. When node 1000 is user equipment 902, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 1000 may be implemented as a blade in a server system when node 1000 is configured as core network element 906. Other implementations are also possible.

[0090] Transceiver 1006 may include any suitable device for sending and/or receiving data. Node 1000 may include one or more transceivers, although only one transceiver 1006 is shown for simplicity of illustration. An antenna 1010 is shown as a possible communication mechanism for node 1000. Multiple antennas and/or arrays of antennas may be utilized. Additionally, examples of node 1000 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 904 may communicate wirelessly to user equipment 902 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 906. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0091] As shown in FIG. 10, node 1000 may include processor 1002. Although only one processor is shown, it is understood that multiple processors can be included. Processor 1002 may include microprocessors, microcontrollers, DSPs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 1002 may be a hardware device having one or many processing cores. Processor 1002 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. Processor 1002 may be a baseband chip, such as baseband chip 802 in FIG. 8. The node 1000 may also include other processors, not shown, such as a central processing unit of the device, a graphics processor, or the like. The processor 1002 may include internal memory (not shown in FIG. 10) that may serve as memory for L2 data. Processor 1002 may include a radio frequency chip, for example, integrated into a baseband chip, or a radio frequency chip may be provided separately. Processor 1002 may be configured to operate as a modem of node 1000, or may be one element or component of a modem. Other arrangements and configurations are also permitted.

[0092] As shown in FIG. 10, node 1000 may also include memory 1004. Although only one memory is shown, it is understood that multiple memories can be included. Memory 1004 can broadly include both memory and storage. For example, memory 1004 may include random-access memory (RAM), read-only memory (ROM), SRAM, dynamic RAM (DRAM), ferro-electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 1002. Broadly, memory 1004 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium. The memory 1004 can be the external memory 808 in FIG. 8. The memory 1004 may be shared by processor 1002 and other components of node 1000, such as the unillustrated graphic processor or central processing unit.

[0093] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 1000 in FIG. 10. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0094] According to an aspect of the present disclosure, a baseband chip can include at least one memory configured to store at least a descriptor of a first packet segment having a first segment offset value. The baseband chip can also include a de-segmentation circuit configured to compare a second segment offset value of a second packet segment to the first segment offset value. The de-segmentation circuit can be configured to store a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value.

[0095] In some embodiments, the de-segmentation circuit can be configured to, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is subsequent to the first packet segment, store the descriptor of the second packet segment after the descriptor of the first packet segment.

[0096] In some embodiments, the de-segmentation circuit can be configured to, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is prior to the first packet segment within an order of segments of a packet comprising the first packet segment and the second packet segment, move down the descriptor of the first packet segment in the at least one memory.

[0097] In some embodiments, the de-segmentation circuit can be configured to move down the descriptor of the first packet segment from a first location of the descriptor in a memory by writing the descriptor in a continguously next location following the first location and can be configured to treat the first location as available.

[0098] In some embodiments, the de-segmentation circuit can be further configured to, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is prior to the first packet segment, compare the second segment offset value to a third segment offset value of a third packet segment stored in the memory immediately above the first packet segment.

[0099] In some embodiments, the de-segmentation circuit can be configured to sort a plurality of segments including the first packet segment and the second packet segment based on comparisons of respective segment offsets of each of the plurality of segments.

[0100] In some embodiments, the de-segmentation circuit is further configured to discard the descriptor of at least one further segment when a comparison of the descriptor of the at least one further segment indicates a duplicate segment to an already stored descriptor.

[0101] In some embodiments, the de-segmentation circuit may be further configured to verify that de segmentation is complete based on segment offset and payload length fields of a plurality of descriptors of a plurality of packet segments comprising the first packet segment and the second packet segment.

[0102] In some embodiments, the verification that de-segmentation is complete can be performed in parallel with comparisons of segment offset values for sorting packet descriptors including the descriptor of the first packet segment and the descriptor of the second packet segment.

[0103] In some embodiments, the de-segmentation circuit can be further configured to pass an ordered list of a plurality of packet descriptors including the descriptor of the first packet segment and the descriptor of the second packet segment to a further module upon verification that de-segmentation is complete.

[0104] According to another aspect of the present disclosure, a method can include storing at least a descriptor of a first packet segment having a first segment offset value in at least one memory. The method can also include comparing, by a de-segmentation circuit, a second segment offset value of a second packet segment to the first segment offset value. The method can further include storing, by the de-segmentation circuit, a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value. [0105] In some embodiments, the method can include, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is subsequent to the first packet segment, storing, by the de-segmentation circuit, the descriptor of the second packet segment after the descriptor of the first packet segment.

[0106] In some embodiments, the method can include, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is prior to the first packet segment, moving down, by the de-segmentation circuit, the descriptor of the first packet segment in the at least one memory.

[0107] In some embodiments, the method can include, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is prior to the first packet segment, comparing, by the de-segmentation circuit, the second segment offset value to a third segment offset value of a third packet segment stored in the memory immediately above the first packet segment.

[0108] In some embodiments, the method can include sorting, by the de-segmentation circuit, a plurality of segments including the first packet segment and the second packet segment based on comparisons of respective segment offsets of each of the plurality of segments.

[0109] In some embodiments, the method can include discarding, by the de-segmentation circuit, a descriptor of at least one further segment when a comparison of the descriptor of the at least one further segment indicates a duplicate segment to an already stored descriptor. [0110] In some embodiments, the method can include verifying, by the de-segmentation circuit, that de segmentation is complete based on segment offset and payload length fields of a plurality of descriptors of a plurality of packet segments comprising the first packet segment and the second packet segment.

[0111] In some embodiments, the verification that de-segmentation is complete can be performed in parallel with comparisons of segment offset values for sorting packet descriptors including the descriptor of the first packet segment and the descriptor of the second packet segment.

[0112] In some embodiments, the method can include passing, by the de-segmentation circuit, an ordered list of a plurality of packet descriptors including the descriptor of the first packet segment and the descriptor of the second packet segment to a further module upon verification that de-segmentation is complete.

[0113] According to a further aspect of the present disclosure, an apparatus for de-segmentation can include means for storing at least a descriptor of a first packet segment having a first segment offset value. The apparatus can further include means for comparing a second segment offset value of a second packet segment to the first segment offset value. The apparatus can additionally include means for storing a descriptor of the second packet segment in the means for storing in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value.

[0114] According to yet another aspect of the present disclosure, a non-transitory computer-readable medium can be encoded with instructions that, when executed in hardware, perform a process. The process can include storing at least a descriptor of a first packet segment having a first segment offset value in at least one memory. The process can further include comparing a second segment offset value of a second packet segment to the first segment offset value. The process can additionally include storing a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value.

[0115] According to still another aspect of the present disclosure, a baseband chip can include at least one memory configured to store at least a descriptor of a first packet segment having a first segment offset value. The baseband chip can also include at least one processor configured to compare a second segment offset value of a second packet segment to the first segment offset value. The at least one processor can be configured to store a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value.

[0116] In some embodiments, the at least one processor can be configured to, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is subsequent to the first packet segment, store the descriptor of the second packet segment after the descriptor of the first packet segment. [0117] In some embodiments, the at least one processor can be configured to, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is prior to the first packet segment, move down the descriptor of the first packet segment in the at least one memory.

[0118] In some embodiments, the at least one processor can be further configured to, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is prior to the first packet segment, compare the second segment offset value to a third segment offset value of a third packet segment stored in the memory immediately above the first packet segment.

[0119] In some embodiments, the at least one processor can be configured to sort a plurality of segments including the first packet segment and the second packet segment based on comparisons of respective segment offsets of each of the plurality of segments.

[0120] In some embodiments, the at least one processor is further configured to discard the descriptor of at least one further segment when a comparison of the descriptor of the at least one further segment indicates a duplicate segment to an already stored descriptor.

[0121] In some embodiments, the at least one processor may be further configured to verify that de segmentation is complete based on segment offset and payload length fields of a plurality of descriptors of a plurality of packet segments comprising the first packet segment and the second packet segment.

[0122] In some embodiments, the verification that de-segmentation is complete can be performed in parallel with comparisons of segment offset values for sorting packet descriptors including the descriptor of the first packet segment and the descriptor of the second packet segment.

[0123] In some embodiments, the at least one processor can be further configured to pass an ordered list of a plurality of packet descriptors including the descriptor of the first packet segment and the descriptor of the second packet segment to a further module upon verification that de-segmentation is complete.

[0124] According to yet another aspect of the present disclosure, a method can include storing at least a descriptor of a first packet segment having a first segment offset value in at least one memory. The method can also include comparing, by at least one processor, a second segment offset value of a second packet segment to the first segment offset value. The method can further include storing, by the at least one processor, a descriptor of the second packet segment in the at least one memory in a position relative to the descriptor of the first packet segment based on the comparison between the first segment offset value and the second segment offset value. [0125] In some embodiments, the method can include, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is subsequent to the first packet segment, storing, by the at least one processor, the descriptor of the second packet segment after the descriptor of the first packet segment.

[0126] In some embodiments, the method can include, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is prior to the first packet segment, moving down, by the at least one processor, the descriptor of the first packet segment in the at least one memory.

[0127] In some embodiments, the method can include, when the comparison of the first segment offset and the second segment offset indicates that the second packet segment is prior to the first packet segment, comparing, by the at least one processor, the second segment offset value to a third segment offset value of a third packet segment stored in the memory immediately above the first packet segment.

[0128] In some embodiments, the method can include sorting, by the at least one processor, a plurality of segments including the first packet segment and the second packet segment based on comparisons of respective segment offsets of each of the plurality of segments.

[0129] In some embodiments, the method can include discarding, by the at least one processor, a descriptor of at least one further segment when a comparison of the descriptor of the at least one further segment indicates a duplicate segment to an already stored descriptor.

[0130] In some embodiments, the method can include verifying, by the at least one processor, that de segmentation is complete based on segment offset and payload length fields of a plurality of descriptors of a plurality of packet segments comprising the first packet segment and the second packet segment.

[0131] In some embodiments, the verification that de-segmentation is complete can be performed in parallel with comparisons of segment offset values for sorting packet descriptors including the descriptor of the first packet segment and the descriptor of the second packet segment.

[0132] In some embodiments, the method can include passing, by the at least one processor, an ordered list of a plurality of packet descriptors including the descriptor of the first packet segment and the descriptor of the second packet segment to a further module upon verification that de-segmentation is complete.

[0133] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0134] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0135] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0136] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, some embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0137] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.