METHOD OF AUTHENTICATING INTERLOCK FUNCTION OF PLC CONTROL PROGRAM USING SMV

Title:

METHOD OF AUTHENTICATING INTERLOCK FUNCTION OF PLC CONTROL PROGRAM USING SMV

Document Type and Number:

WIPO Patent Application WO/2014/030854

Kind Code:

A1

Abstract:

A method of authenticating an interlock function of a PLC control program executed in a PLC driving system controlling an automated production system is disclosed. The method of authenticating the interlock function of the PLC control program according to an embodiment of the present invention includes: converting the PLC control program into a control intermediate model which represents an output signal as a parent node and state change logics affecting a state change of the output signal as child nodes; simplifying the control intermediate model by using information on a list of output signals that are simultaneously turned ON from among a plurality of output signals output from the PLC driving system as the PLC control program is executed and causing an error situation during the operation of the automated production system; converting the PLC driving system and the simplified control intermediate model into a finite state machine (FSM) type model; and performing relay authentication that determines whether output signals in the list of output signals causing the error situation are simultaneously turned ON, by the simplified control intermediate model converted into the FSM type model by using a symbolic model checker (SMV), in order to correct the PLC control program so that an interlock function for preventing the error situation is implemented.

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Inventors:

PARK CHANG MOK (KR)
WANG JI NAM (KR)

Application Number:

PCT/KR2013/006857

Publication Date:

February 27, 2014

Filing Date:

July 31, 2013

Export Citation:

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Assignee:

UDMTEK CO LTD (KR)

International Classes:

G05B19/05; G05B17/00

Domestic Patent References:

WO2010071101A1

2010-06-24

Foreign References:

KR20100054947A	2010-05-26
KR20040041906A	2004-05-20

Other References:

JEE, EUN KYOUNG ET AL.: "A Formal Verification Technique for PLC Programs Implemented with Function Block Diagrams", JOURNAL OF THE KOREA INFORMATION SCIENCE SOCIETY: COMPUTING PRACTICES AND LETTERS, vol. 15, no. 3, March 2009 (2009-03-01)

Attorney, Agent or Firm:

YOON, JAE SEUNG (KR)
윤재승 (KR)

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