Title:
METHOD AND CIRCUITS FOR REDUCING NOISE IN PHASE-LOCKED LOOPS
Document Type and Number:
WIPO Patent Application WO/2021/146476
Kind Code:
A3
Abstract:
A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the reference input signal; a charge pump coupled to the phase frequency detector and configured to convert the one or more comparison signals into a driving current; a loop filter coupled to the charge pump and configured to split the driving current to generate a first voltage signal and a second voltage signal; and a voltage controlled oscillator coupled to the loop filter and configured to: receive the first voltage signal and generate a first control current; receive the second voltage signal and generate a second control current; and combine the first and second control currents to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.
Inventors:
BHAGWAN RAGHUNAND (US)
ROGERS ALAN (US)
ROGERS ALAN (US)
Application Number:
PCT/US2021/013507
Publication Date:
September 10, 2021
Filing Date:
January 14, 2021
Export Citation:
Assignee:
ANALOG BITS INC (US)
International Classes:
H03L7/089; H03L7/099; H03L7/18
Foreign References:
| US20070030078A1 | 2007-02-08 |
Attorney, Agent or Firm:
GOREN, David J. et al. (US)
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