METHOD OF FORMING A LOW-K DUAL DAMASCENE INTERCONNECT STRUCTURE

Title:

METHOD OF FORMING A LOW-K DUAL DAMASCENE INTERCONNECT STRUCTURE

Document Type and Number:

WIPO Patent Application WO2004061916

Kind Code:

A3

Abstract:

A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Inventors:

DELGADINO GERARDO A
YE YAN
SHIN NEUNGHO
KIM YUNSANG
XIA LI-QUN
HUANG TZU-FANG
LI LIHUA
CHIU JOEY
ZHAO XIAOYE
TIAN FANG
ZHU WEN
YIEH ELLIE

Application Number:

PCT/US2003/041145

Publication Date:

September 16, 2004

Filing Date:

December 23, 2003

Export Citation:

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Assignee:

APPLIED MATERIALS INC (US)

International Classes:

H01L21/768; (IPC1-7): H01L21/768

Foreign References:

US20020102856A1	2002-08-01
US20020187627A1	2002-12-12
US5950106A	1999-09-07

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