METHOD OF MANUFACTURE AND RESULTING STRUCTURES FOR

SEMICONDUCTOR DEVICES FIELD OF INVENTION

The present invention generally relates to integrated circuits and the manufacture of semiconductor devices. In particular, the present invention relates to the fabrication of semiconductor wafer/metallic substrate assemblies, referred to herein as composite wafers, used for semiconductor devices and the preparation of semiconductor devices per se as well as the preparation of materials generally by way of cutting and/or removing material. In one form, the invention is suitable for use in manufacturing processes relating to metal- insulator-semiconductor (MIS) heterojunction bipolar transistors (HBT's) comprising compound semiconductor materials such as gallium arsenide (GaAs) and it will be convenient to hereinafter describe the invention in relation to that application, It should be appreciated, however, that the present invention is not limited to that application, only. For example, the invention is also suitable for use in relation to semiconductor devices comprising other compound semiconductors such as indium phosphide (InP) and gallium nitride (GaN). BACKGROUND

The inventor has identified the following related art. Modern radio systems are designed to obtain maximum utilisation from scarce frequency spectrum resources. To do this, radio transmitters may be required to produce complex waveforms which encode data in a highly efficient manner on carrier signals. This, in turn, may require amplifying circuits with high power and high linearity at high frequency. Silicon-based circuitry cannot easily meet the demands of these applications in frequency bands above 1GHz and as a result, semiconductors made from compound semiconductors such as gallium arsenide may be used in preference.

Semiconductor device designers have appreciated the importance of bandgap engineering in designing transistor devices for high performance applications. Bandgap engineering may generally be referred to as the art of creating semiconductor junctions from materials which have similar crystal structures but different intrinsic electron energy levels. Junctions formed from

different materiafs are commonly referred to as heterojunctions. It has been realised that electron transport across these junctions may be enhanced by the appropriate selection of materials.

Compound semiconductor material systems based on, for example, gallium arsenide (GaAs), indium phosphide (InP) and other elemental compounds may be used as the basis on which heterojunctions can be formed and from which devices such as ultra-high performance transistors can be built. In this particular example, single crystal boules made from materials such as GaAs may be grown and sliced to form wafer substrates. Layers of different materials may be epitaxially grown on the surface of these wafers and then patterned by etching to form devices such as Heterojunction Bipolar Transistors (HBT's). These devices are made from layers of different materials which are doped with impurities to make them electron-rich (n-type) or electron-deficient (p-type). In this way, desirable p-n junctions may be formed which enhance charge carrier transport within the transistor.

Generally, on gallium arsenide wafers, for example, conventional heterojunctions may be formed using layers of materials such as indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), aluminium gallium arsenide (AIGaAs) and aluminium arsenide (AIAs). On indium phosphide wafers, heterojunctions may be formed using indium gallium arsenide material. In each case the bandgap and energy band offset of the heterojunction may be controlled by changing the relative proportions of elemental constituents of the material. Although there have been significant improvements in conventional devices, many limitations still exist and additional improvement is desired, Figure 1 shows a typical layer structure used to form conventional npn

GaAs based HBT's. Typically, layer structures are devised which not only achieve the desired electronic properties of a transistor but which also offer wafer processing advantages such as what may be referred to as selective etching. Selective etching techniques allow one layer to be removed in certain areas of the wafer without affecting underlying or surrounding layers. This may be particularly important in controlling etching processes which need to stop abruptly on the boundaries of layers which might be very thin (e.g. 100 - 500 angstroms). In this

regard the inventor recognises that transistor performance may not only be determined by the choice of layer material but also layer thickness. Selection of layer thickness may sometimes involve a compromise between certain transistor parameters. For example, in conventional devices, high speed devices often need thin layers to shorten electron transit times while high power devices generally need thick layers to withstand high voltages. Therefore, in general, it may not be possible to completely optimise a conventional transistor for both high speed and high operating voltage. Typical layer thicknesses for related art npn GaAs / InGaP HBT devices are also shown in Figure 1. Figure 2 shows an example of a certain conventional device structure. In this example, the emitter mesa structure 200 is comprised of four semiconductor layers:

• layer 204 forms the emitter side of the emitter/base heterojunction and is made of a material which has different etching characteristics than the adjacent layers,

• layer 203 is a buffer / spacer layer,

• layer 202 is a graded structure which varies from the crystal lattice spacing of GaAs at the interface with layer 203 to the lattice spacing of InGaAs (50% Ga) at the interface with layer 201 , and • layer 201 which allows a non-alloyed ohmic contact to be made to the emitter structure.

The emitter mesa 200 may be formed by firstly depositing and patterning emitter contact layer 205 on the surface of a wafer which has a layer structure as shown generally in Figure 1. Next, emitter layers 201 , 202 and 203 are etched away except where protected by the emitter contact 205. Etching stops at layer 204 because it is unaffected by the etchant used to remove layers 201 - 203. However etching may continue horizontally and helps to produce undercut sidewalls of the emitter mesa structure.

Layer 204 is then removed using an etchant which does not affect the underlying base layer 207. In this way, the emitter mesa can be formed without degrading the very thin base layer 207.

The base contact layer 206 may be deposited over the entire base and emitter area using a directional deposition process. Since the sidewalls of the emitter mesa structure are under-cut, the emitter contact layer 205 creates a shadow which allows the base contact layer 206b to be deposited in close proximity to the emitter without touching it, except harmlessly on top of the emitter σhmic, 206a. In this fashion, conventional devices may achieve self alignment of base emitter junction connections thereby enhancing device performance by minimising base spreading resistance.

From a first perspective, the inventor has identified that although transistors made from materials such as, for example, gallium arsenide have certain attractive features in high frequency RF circuits, other aspects of these devices create problems for circuit designers.

For example compound semiconductor transistors create difficulties in the design of power amplifiers for battery powered devices such as mobile phones. Batteries in these portable devices typically provide power supply voltages in the range 3 to 4 volts. This creates a problem for devices made from compound semiconductors such as GaAs because of the relatively high turn on voltages for transistors made from these materials. For example, conventional GaAs HBT's have a turn on voltage of around 1.3 to 1.4 volts. This is a significant fraction of the total power supply and circuit designs may be restricted to no more than two base-emitter junctions in series. Even when this circuit requirement is met, it may be possible for circuits to fail at low temperatures given that turn on voltages generally increase with lowered temperatures. For the purposes of this disclosure, "turn-on voltage" may be defined here as the voltage which needs to be ^' applied to the base emitter junction of a transistor to achieve 1 % of the maximum rated transistor current flowing from collector to emitter.

The inventor has identified prior attempts in the field relating to reduction of the turn on voltage of compound semiconductor HBTS. For example, US patent 6750480: "Bipolar transistor with lattice matched base layer" issued to Welser et al relates to the use of dilute nitrides such as InGaAsN where relatively small amounts of indium are introduced into the GaAs material to reduce the bandgap (and hence turn on voltage) and small amounts of nitrogen are introduced to

relieve stress caused by the larger crystal lattice constant of InGaAs compared to GaAs. However, it appears, from the disclosure of Welser et al, as evidenced by the considerable effort involved in growing materials such as InGaAsN, that there may be a belief in the industry that it is necessary to maintain mono-crystalline structure across the emitter-base and base-collector junctions of a device.

From a different perspective, transistors known as Tunnelling Emitter Bipolar Transistors (TEBTs) exist in related art. US patent 4845541 issued to Xu et al describes one such TEBT and is incorporated by reference herein. These devices use tunnelling barriers at the emitter base junction to enhance electron injection into the device thereby improving its DC and high frequency characteristics. The Xu patent uses intrinsic AIGaAs as a tunnel barrier on a device with a GaAs base layer. Other references such as the paper "High- Current-Gain Small-Offset-Voltage InGaPfGaAs Tunnelling Emitter Bipolar Transistors Grown By Gas Source Molecular Beam Epitaxy, Lu et al, IEEE Electron Devices Letters, Vo1 13, No 9, 1992" describes the use of tunnel barriers formed using InGaP on GaAs. Other references such as the paper "DC Characterization of InP/inGaAs Tunnelling Emitter Bipolar Transistor, Cheng et al, Japan Society of Applied Physics, VoI 44, No.2, 2005" describe the use of InP as the tunnel barrier on a device with an InGaAs base layer. Again, from the above noted disclosures, it appears there is an emphasis on the importance with regard to TEBTs to maintain a mono crystalline structure across the emitter-base and base-collector junctions.

A different class of HBT device exists in related art that may generally be referred to as a Metal Semiconductor Insulator (MIS) transistor. These devices use metals and ultra thin insulators to form the emitter structure of transistors. A description of certain fundamental principles involved in using MIS structures for silicon bipolar transistors of this class of transistor, in particular, may be found in the paper: "Super-Gain Silicon MIS Heterojunction Emitter Transistors" M.A. Green, et al, IEEE Electron Device Letters, vol. EDL-4, NoJ, pp 225-227, July 1983. The emitters of these devices are made from low work-function metals such as magnesium, deposited on top of ultra thin silicon dioxide insulating layers approximately 20 angstroms thick.

A band diagram of the base-emitter junction for an MIS type of transistor is shown under zero bias conditions in Figure 3. As illustrated in figure 3, a low work function metal is chosen for the emitter such that electrons can tunnel from the metal's conduction band, through the insulating layer and into the p-type base layer, forming a pseudo-n-type inversion layer. Because of the band structure of this type of junction, emitter-base current flow is predominantly due to electron tunnelling from emitter to base and hole injection from base to emitter may be effectively blocked. This may enhance transistor current gain and also may reduce sources of noise generation. Silicon transistors with current gains as high as 25,000 have been reported.

The inventor has recognised that for MIS transistors to function properly, it is important that the material chosen for the ultra-thin insulator is chemically stable and is able to be deposited in very thin layers, for example 10 to 20 angstroms, with high degrees of uniformity across an entire semiconductor wafer. If there are non-uniformities such as "pin holes" in the insulating layer, transistors made from these layers may not function.

It is also important that the insulating layer has well defined electronic properties and atomic band structure. The band structure of the insulating layer may be considered critical in controlling the flow of charge carriers (electrons and/or holes) through the transistor.

Generally, it is considered that the band structure of metallic oxides may be favourable for creating suitable insulating layers for MIS transistors.

However, the inventor has found that insulating layers made by evaporating solid sources of metallic oxides onto the surface of wafers are likely to have poor stoichiometry and hence poorly defined band structure. In the evaporation process, which is typically performed using an electron beam evaporator, the solid oxide material decomposes to form oxygen which escapes from the system, for example, via chamber vacuum pumps. Hence oxides deposited using evaporation of solid sources tend to be oxygen deficient which alters their band structure.

Other approaches for oxide deposition such as sputtering may also tend to produce oxygen deficient insulating layers.

In addition, in processing wafers to make transistors, the insulating layer may be exposed to water and other reactive chemicals that may affect change or even remove the insulating layer. Some oxides provide useful band properties as deposited, but degrade quickly in contact with aqueous solutions or even exposure to the atmosphere.

The structure of a prior art MIS transistor is shown in Figure 4. This structure is very similar to conventional HBT structures except that the emitter 400 is formed by an ultra thin insulator 404 and one or more metal layers 402, 403 which are chosen for their characteristics, notably work function, chemical stability and conductivity.

Any discussion of documents, devices, acts or knowledge in this specification is included to explain the context of the invention, It should not be taken as an admission that any of the material forms a part of the prior art base or the common general knowledge in the relevant art in Australia or elsewhere on or before the priority date of the disclosure and claims herein. SUMMARY OF INVENTION

Certain aspects of the present invention relate to improvements in the methods, devices and apparatus of the disclosures of one or more of US Patent No 6,919,261 , US Patent No 6,960,490, International (PCT) Application No PCT/AU03/00298, published as WO 2003/077311 , International (PCT) No PCT/AU2004/000309, published as WO 2004/082020, and International (PCT) Application No PCT/AU2004/001184, published as WO 2005/022580, each being, commonly assigned to the present applicant and incorporated herein by reference. The inventor has identified that, in a particular respect, it is desirable to provide an improved process of manufacturing MIS HBT devices which provides increased control of insulating layer thickness, uniformity and stoichiomβtry. It is also desirable to provide insulating layers that have relative chemical stability. Furthermore, it is also desirable to provide a manufacturing process for MIS transistors which protects the insulating layer from exposure to chemicals or the atmosphere after it has been deposited,

It is therefore an object of the present invention to provide a method and apparatus which improves the manufacturability of arrangements discussed in the above disclosures and other related art arrangements as discussed herein.

It is also an object of the present invention to provide a method and apparatus, which alleviates at least one disadvantage associated with related art arrangements as discussed herein.

In one preferred aspect the present invention provides a method of forming a base-emitter junction for a heterojunction bipolar transistor device comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a collector region and a base layer operatively coupled to the collector region; introducing a first chemical precursor comprising a first chemical species to the base layer for reacting therewith so as to deposit a first monolayer of the first chemical species; introducing at least a second chemical precursor comprising at least a second chemical species to the first monolayer for reacting therewith so as to form a resultant monolayer wherein the resultant monolayer comprises a compound of the first and second chemical species. In another preferred aspect the present invention provides a method of forming a base-emitter junction for a heterojunction bipolar transistor device comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a collector region and a base layer operatively coupled to the collector region; depositing at least one sub-layer of a first metal over the base layer; exposing the first metal to a form of oxygen so as to substantially oxidise the at least one sub-layer of first metal and thereby form at least a portion of an ultra-thin insulating layer. In a further preferred aspect the present invention provides a method of forming a base-emitter junction for a heterojunction bipolar transistor device comprising the steps of:

providing a layered compound semiconductor material arrangement comprising at least a collector region and a base layer operatively coupled to the collector region; depositing a first and at least a second chemical precursor to provide at least one thin layer of atomically dense metal oxide over the base layer thereby forming a base-emitter junction adapted to provide a tunnelling barrier against free charge carriers located external to the base layer.

In yet another preferred aspect the present invention provides a method of forming a base-emitter junction for a heterojunction bipolar transistor device comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a collector region and a base layer operatively coupled to the collector region; sequentially depositing at least one very thin layer of metal and controllably exposing the at least one deposited metal layer to a form of oxygen to facilitate an oxidation process of the metal layer.

In still another preferred aspect the present invention provides a method of forming a base-emitter junction for a heterojunction bipolar transistor device comprising the steps of: providing a layered compound semiconductor materia! arrangement comprising at least a collector region and a base layer operatively coupled to the collector region; depositing an ultra-thin layer of insulating material over the base layer to form the base-emitter junction wherein the insulating material comprises: a relatively low conduction band barrier for electrons in the range of about

1.4eV to about 2.8eV.

In still another preferred aspect the present invention provides a base- emitter junction for a heterojunction bipolar transistor comprising an ultra-thin layer of insulating material wherein the insulating material is adapted to provide a relatively low conduction band barrier for electrons in the range of about 1.4eV to about 2.8eV.

In a further preferred aspect the present invention provides a heterojunction bipolar transistor structure comprising: a base; an emitter, and; a base-emitter junction adapted to provide a tunnelling barrier between the base and a source of free charge carriers residing in the emitter, wherein the base-emitter junction comprises an ultra-thin insulating layer of atomically dense metal oxide adapted to provide a relatively low conduction band barrier for electrons in the range of about 1.4eV to about 2.8eV. In another preferred aspect the present invention provides a method of manufacturing a compound semiconductor metal-insulator-semiconductor device comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a collector region and a base layer coupled to the collector region; depositing a thin oxide layer over the base layer; depositing a second metal layer over the thin oxide layer; depositing an oxide resistant capping layer over the second metal layer wherein the capping layer is adapted to provide a selective masking means for at least the second metal layer.

In another preferred aspect the present invention provides a method of manufacturing a compound semiconductor metal-insulator-semiconductor device comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a collector region and a base layer coupled to the collector region; depositing a thin oxide layer over the base layer; depositing a second metal layer over the thin oxide layer; depositing a capping layer over the second metal layer; selectively removing a portion of the capping layer to expose a corresponding portion of the second metal layer;

forming a further oxide layer comprising an oxide of the exposed corresponding portion of the second metal layer; selectively removing a portion of the further oxide layer and corresponding portions of the thin oxide layer to expose corresponding portions of the base layer; depositing base contacts on the exposed base layer portions.

In essence, the present aspects described above stem from the realisation that providing an atomically dense layer of metal oxide with properties of stability by virtue of depositing one metal oxide monolayer at a time or depositing a predetermined thickness of metal and then oxidising this thickness and/or in which the specified metal oxide is adapted to provide predetermined bandgap barriers may provide a useful tunnelling barrier in compound semiconductor MIS transistors. Further still the preferred aspects noted above stem from the realisation that a low work function metal of a MIS HBT does not need to be very thick in forming a base-emitter MIS junction allowing the metal to fully oxidise on selective exposure to atmosphere with the use of a protective capping layer to provide a passivating layer that may assist in providing an improved emitter structure in the manufacturing stages.

In one other preferred aspect the present invention provides a heterojunction bipolar transistor structure comprising: a layered compound semiconductor material arrangement comprising at least a subcollector layer and a collector layer operativefy coupled to the subcollector layer such that the crystal structure of the collector layer matches the crystal structure of the subcollector layer; a base layer operatively coupled to the collector layer and adapted to be grown on the collector layer in the form of a crystal structure that differs from the crystal structure of the collector layer.

In another preferred aspect the present invention provides a heterojunction bipolar transistor structure comprising: a base; a collector region; an emitter, and;

a base-emitter junction comprising an ultra-thin layer adapted to provide a tunnelling barrier between at least one type of free charge carrier residing in the emitter or the base and comprising a material having a substantially wide bandgap with respect to the bandgap of a base material; wherein the base comprises a metamorphic structure at or between a base-collector junction and the base-emitter junction.

In a further preferred aspect the present invention provides a heterojunction bipolar transistor structure comprising: a layered compound semiconductor material arrangement comprising at least a subcollector layer and a collector layer operatively coupled to the subcollector layer such that the crystal structure of the collector layer matches the crystal structure of the subcollector layer; a base layer operatively coupled to the collector layer and adapted to be grown on the collector layer in the form of a crystal structure that differs from the crystal structure of the collector layer; a base-collector junction comprising an inter-diffusion region where base material and collector material are diffused into the collector and base respectively.

In yet another preferred aspect the present invention provides a heterojunction bipolar transistor structure comprising: a layered compound semiconductor material arrangement comprising at least a subcollector layer and a collector layer operatively coupled to the subcollector layer such that the crystal structure of the collector layer matches the crystal structure of the subcollector layer; a base layer operatively coupled to the collector layer and adapted to be grown on the collector layer in the form of a crystal structure that differs from the crystal structure of the collector layer; a grading region comprising a graded composition of material wherein the grading region is adjacent a base-collector junction. In still another preferred aspect the present invention provides a heterojunction bipolar transistor comprising:

a subcollector layer grown on a semiconductor substrate such that its crystal structure matches the crystal structure of the substrate a collector layer grown on the subcollector layer such that its crystal structure matches the crystal structure of the subcollector a base layer grown on top of the collector layer with either a constant or variable composition and which has a either a different crystal lattice constant or a different crystal structure, an amorphous or polycrystalline emitter barrier layer grown on top of the base layer, and an emitter contact layer grown on top of the emitter barrier layer which is either amorphous, polycrystalline or metallic.

In yet a further preferred aspect the present invention provides a method of manufacturing a heterojunction bipolar transistor structure comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a subcollector layer and a collector layer operatively coupled to the subcollector layer such that the crystal structure of the collector layer matches the crystal structure of the subcollector layer; growing a base layer over the collector layer wherein the base layer is grown on the collector layer in the form of a crystal structure that differs from the crystal structure of the collector layer.

In a further preferred aspect the present invention provides a method of manufacturing a heterojunction bipolar transistor structure comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a subcollector layer and a collector layer operatively coupled to the subcollector layer such that the crystal structure of the collector layer matches the crystal structure of the subcollector layer; growing a base layer over the collector layer wherein the base layer is grown on the collector layer in the form of a crystal structure that differs from the crystal structure of the collector layer;

applying heat to a base-collector junction to invoke diffusion of base material into the collector and collector material into the base so as to define an inter-diffusion region proximate the base-collector junction.

In another preferred aspect the present invention provides a method of manufacturing a heterojunction bipolar transistor structure comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a subcollector layer and a collector layer operatively coupled to the subcollector layer such that the crystal structure of the collector layer matches the crystal structure of the subcollector layer; growing a base layer over the collector layer wherein the base layer is grown on the collector layer in the form of a crystal structure that differs from the crystal structure of the collector layer; forming a grading region comprising a graded composition of material proximate a base-collector junction.

In a further preferred aspect the present invention provides a method of manufacturing a heterojunction bipolar transistor structure comprising the steps of; selectively etching a layered compound semiconductor structure as disclosed herein.

Importantly, the inventor has realised with particular emphasis on MIS HBTs that it is not necessary to maintain a mono-crystalline device structure across the base-emitter junction in order to obtain desired device performance. The relaxation of this requirement creates numerous possibilities in the choice of base material, which can potentially lead to lower turn on voltages and novel device structures.

In one further preferred aspect the present invention provides a method of manufacturing a composite substrate for semiconductor devices comprising the step of: providing a layer of surface compliant material between a first and second portion of the composite substrate, the layer being adapted to, under application

of pressure, deform and resiliently maintain its deformation in accordance with opposing first surfaces of the first and second portions.

Accordingly, in this preferred aspect the present invention provides a method of manufacture for composite wafers where a single temporary carrier substrate is used both to support a semiconductor wafer while it is thinned and while it is being subsequently bonded to a metallic substrate.

This preferred aspect of the present invention stems from the realisation that semiconductor wafers, particularly those made from compound semiconductor materials, are very fragile after they have been thinned and need to be continually supported until they are bonded to a permanent supporting structure (i.e. a metal substrate).

In another preferred aspect the present invention provides a surface compliant material for use in manufacturing a composite substrate for semiconductor devices wherein the material has characteristics which comprise: a structural compliance for yielding under pressure so as to deform against contacted surfaces; a denaturing temperature substantially greater than the eutectic temperature of a bonding metal alloy used for bonding a semiconductor wafer to a substantially metallic alloy substrate of the composite substrate. Embodiments of the present invention provide a structure for supporting a semiconductor wafer on a rigid temporary carrier for thinning and subsequent bonding to a metal substrate where the adhesive used to bond the wafer to the temporary carrier is compliant at the temperature of bonding the wafer to the substrate. This preferred aspect of the present invention stems from the realisation that it is advantageous to have a non-rigid, elastic or compliant material between the temporary substrate used to mount a semiconductor wafer for thinning and the wafer itself so that when force is applied to the wafer during the eutectic bonding process used to form the composite wafer, the compliant material flows to distribute bond pressure evenly.

In another preferred aspect the present invention provides a composition for use in forming at least one bonding layer in a semiconductor manufacturing process, the composition comprising; a eutectic metal alloy having a eutectic temperature lower than the denaturing temperature of a temporary adhesive material for use in temporarily adhering a semiconductor wafer to a temporary carrier for the wafer.

Embodiments of the present invention provide a method of bonding a semiconductor wafer to a metal substrate using a eutectic bond layer which bonds the semiconductor wafer to a metal substrate at a temperature which is low enough to prevent deterioration of the adhesive used to support the wafer on a temporary carrier.

This preferred aspect of the present invention stems from the realisation that the adhesive used to bond semiconductor wafers to temporary substrates for thinning is preferably an organic material such as a glue and that these materials can decompose at elevated temperatures needed for eutectic bonding causing them to lose their desirable adhesive properties and making them difficult to remove.

In another preferred aspect the present invention provides a method of manufacturing a composite substrate for use in fabricating semiconductor devices comprising the step of: providing a temporary carrier operatively associated with a semiconductor wafer; providing a substrate for supporting the semiconductor wafer of the composite substrate; providing a bonding layer to each of respective opposing surfaces of the semiconductor wafer and the substrate for bonding the semiconductor wafer to the substrate wherein at least one of the bonding layers comprises a eutectic metal alloy with a eutectic temperature lower than the denaturing temperature of a temporary adhesive material for use in temporarily adhering the wafer to the temporary carrier.

In another preferred aspect the present invention provides a method of bonding a first portion of a composite substrate with a second portion of a

composite substrate in a semiconductor manufacturing process, the method comprising the steps of: providing, with the first portion, a temporary adhesive layer for temporarily adhering the first portion to a temporary carrier operatively associated with the first portion; applying to the first and second portions, a respective first and second layer of bonding material; disposing the first and second bonding layers into contact with each other; activating bonding between the first and second bonding layers. In another preferred aspect the present invention provides a method of manufacturing a composite substrate for semiconductor devices, the method comprising the steps of: bonding a semiconductor wafer to at least a metal substrate to provide the composite substrate and; subsequently applying a further process to a portion of the composite substrate.

Embodiments of the present invention in accordance with this preferred aspect provide a means of dressing the edge of a semiconductor wafer which is bonded to a metal substrate to eliminate the possibility of epitaxial layers on the surface of the wafer coming into electrical contact with the metal substrate.

This preferred aspect of the present invention stems from the realisation that when a semiconductor wafer is thinned and then bonded to a metal substrate to form a composite wafer assembly, there is a strong possibility that epilayers present on the surface of the wafer can come into electrical contact with the metal substrate around the perimeter of the wafer, thereby forming a structure which has unwanted electrolytic behaviour during fabrication process steps such as etching.

Further embodiments in accordance with this preferred aspect of the present invention provides a means of preventing unwanted electrolytic effects in etching processes performed on the composite wafer.

This preferred aspect of the present invention stems form the realisation that an electro-potential can be created between the metal substrate and the

semiconductor surface when the composite wafer is processed in aqueous etching solutions, and that this potential can make etching processes uncontrollable.

In a further preferred aspect the present invention provides a layered material arrangement for a composite substrate suitable for use in fabricating semiconductor devices comprising: a semiconductive wafer; a substantially metallic substrate for supporting the semiconductive wafer, and: a bonding layer between the metallic substrate and the wafer for bonding the wafer to the metallic substrate, wherein the maximum particle size of the material of the metallic substrate is less than about 2μm.

In another preferred aspect the present invention provides a method of providing a layered material arrangement for a composite substrate suitable for use in fabricating semiconductor devices comprising the steps of: providing a semiconductive wafer; providing a substantially metallic substrate for supporting the semiconductive wafer, and: providing a bonding layer between the metallic substrate and the wafer for bonding the wafer to the metallic substrate, wherein the maximum particle size of the material of the metallic substrate is less than about 2μm.

In another preferred aspect the present invention provides a method of preparing the surface of a substrate, where the substrate comprises a particulate matrix of at least a first substantially hard material and at least a second substantially soft materia! interspersed within the matrix, the method comprising the steps of: applying an abrasive element operating in accordance with a first controlled motion to the surface in accordance with a second controlled motion.

Embodiments of the present invention in accordance with the above preferred aspects provide a method of preparing a metal substrate for use in a composite wafer assembly such that the surface to be bonded is very flat.

This preferred aspect of the present invention stems from the realisations that if the metal substrate is not flat, defects can potentially occur in the eutectic bond layer and photolithography performed on the composite wafer will be impaired because the surface is not flat. Further embodiments of the present invention in accordance with the above preferred aspects provide a method of preparing a metal substrate for use in a composite wafer assembly such that the surface to be bonded is free from significant defects.

This preferred aspect of the present invention stems from the realisations that controlled thermal expansion metal substrates made form infiltrated metal components can have voids in the material that are created during forming the bulk metal substrate material or in polishing the surface.

In another preferred aspect the present invention provides a method of manufacturing a composite substrate suitable for use in fabricating semiconductor devices, the method comprising the steps of: providing at least one bond structure(s) between a first and second portion of the composite substrate, the bond structure(s) being adapted to, under application of heat and when the first and second portions are bought into proximity with each other, flow into space between opposing first surfaces of the first and second portions.

In another preferred aspect the present invention provides a composite substrate suitable for use in fabricating semiconductor devices comprising: a semiconductor wafer and a substantially metallic substrate, each comprising opposing first surfaces and; a structured bonding portion between the opposing first surfaces of the semiconductor wafer and the metallic substrate, the structured bonding portion comprising: a first bond substrate layer deposited on one opposing first surface; a second substantially metallic bond layer patterned on the first bond substrate layer; a third substantially metallic bond layer deposited on the second substantially metallic bond layer wherein the third substantially metallic bond layer

is adapted to, under application of heat, deform whilst remaining at least partially adhered to patterned formations of the second metallic bond layer and form a metallic bond between the semiconductor wafer and the metallic substrate when heated in contact with a fourth bond layer disposed on the other opposing first surface.

Embodiments of the present invention in accordance with the above preferred aspects provide a means of bonding semiconductor wafers to metal substrates where the bond layer is patterned to form features which improve bond uniformity, minimise the occurrence of voids in the bond layer and reduce physical stress on the semiconductor layer of the composite wafer.

This preferred aspect of the present invention stems form the realisation that the eutectic bonding process requires that the two surfaces to be bonded are in intimate contact during bonding and that surface imperfections or irregularities can prevent this from occurring. In addition, this preferred aspect stems from the realisation that the alloyed bond layer can create mechanical stresses on the semiconductor layer and that this stress can affect the overall reliability of the composite wafer.

In another preferred aspect the present invention provides a method of manufacturing a composite substrate suitable for use in fabricating semiconductor devices comprising the steps of: providing an attenuation region between a semiconductor wafer and at least one bonding layer, the bonding layer being adapted to, under application of heat, form a metallic bond between the semiconductor wafer and a substantially metallic substrate wherein the attenuation region is substantially inactive with respect to the formation of the metallic bond such that the attenuation region is adapted to attenuate the semiconductor wafer from stress(es) in the bonding layer.

In another preferred aspect the present invention provides a composite substrate suitable for use in fabricating semiconductor devices comprising: a semiconductor wafer; an attenuation region in operative association with the semiconductor wafer;

at least one bonding layer adapted to, under application of heat, form a metallic bond between the semiconductor wafer and a substantially metallic substrate wherein the attenuation region is adapted to attenuate the semiconductor wafer from stresses formed in the bonding layer under formation of a bond with the metallic substrate.

Embodiments of the present invention in accordance with the above preferred aspects provide an alternate means of reducing mechanical stress on the semiconductor layer in a composite wafer.

This preferred aspect of the present invention stems form the realisation that the eutectic material which forms during bonding can expand, thereby putting the semiconductor wafer under stress.

In another preferred aspect the present invention provides a method of manufacturing a composite substrate suitable for use in fabricating an electronic circuit, the method comprising the steps of: providing a semiconductor wafer layer; providing a substantially metallic substrate layer; providing a metallic bond layer for bonding the semiconductor layer with the substantially metallic substrate, and; intermediate the semiconductor wafer layer and the substantially metallic substrate layer, providing a further layer which is substantially non-passivating with respect to the formation of etched via structures.

In a further preferred aspect the present invention provides a composite substrate suitable for use in fabricating electronic circuits comprising: a semiconductor wafer layer; a substantially metallic substrate layer; at least one metallic bond layer for bonding the semiconductor wafer layer with the substantially metallic substrate layer, and; intermediate the semiconductor wafer layer and the substantially metallic substrate layer, a further layer which is substantially non-passivating with respect to the formation of etched via structures,

Embodiments of the present invention in accordance with the above preferred aspects provide a means of improving electrical contacts made from the semiconductor layer of the composite wafer to the underlying metal substrate.

This preferred aspect of the present invention stems form the realisation that when via holes are made in the semiconductor layer to create electrical contacts to the underlying metal substrate, the metal layer exposed at the bottom of the via hole during the etching process must be free from degradation that could prevent low resistance contacts being made to the metal substrate.

In another preferred aspect the present invention provides a method of fabricating an electronic circuit comprising the steps of: forming a composite substrate comprising a semiconductor wafer bonded to a substantially metallic substrate; forming via structures within the semiconductor wafer to expose the metallic substrate; applying a filling material to the surface of the composite substrate; further processing the substrate such that the filling material remains substantially only within the vicinity of the via structures of the surface of the composite substrate; applying photoresist to the surface of the composite substrate. In a further preferred aspect the present invention provides a method of fabricating an electronic circuit comprising the steps of: forming a composite substrate comprising a semiconductor wafer bonded to a substantially metallic substrate; forming dicing lanes within the surface of the semiconductor wafer wherein the dicing lanes define chip pedestals and the dicing lanes are formed such that the chip pedestals comprise at least one edge which is at least partially curved.

Embodiments of the present invention in accordance with the above preferred aspects provide means of performing photolithography on the surface" of a composite wafer after portions of the semiconductor wafer have been removed to expose the underlying metal substrate,

This preferred aspect of the present invention stems from the realisation that when structures such as via holes are made in the semiconductor wafer

component of a composite wafer, it is difficult to perform photolithography on the surface of the composite wafer because of the relatively deep surface topology.

In yet a further preferred aspect the present invention provides a method of removing material comprising the steps of: guiding a beam of radiation through a controlled stream of radiation transmissive fluid to a point of removal on the material; removing material at the removal point by thermal ablation induced by the radiation interacting with the material at the point of removal.

In a further preferred aspect the present invention provides a method removing material comprising the steps of: guiding a beam of radiation through a controlled stream of radiation transmissive fluid to a point of removal on the material; removing material at the removal point by chemical etching induced by the radiation interacting with the fluid at the point of removal. In another preferred aspect the present invention provides a method of removing material comprising the steps of: guiding a beam of radiation through a controlled stream of radiation transmissive fluid to a point of removal on the material; removing material at the removal point by thermal ablation induced by the radiation interacting with the material and by chemical etching induced by the radiation interacting with the fluid at the cutting point.

In a further preferred aspect the present invention provides a method of cutting a substrate to provide integrated circuit chips, the substrate comprising at least a semiconductor wafer, the method comprising the steps of: guiding a beam of radiation within a controlled stream of radiation transmissive fluid to a cutting point on the substrate; removing substrate material at the cutting point by thermal ablation induced by the radiation interacting with the substrate material at the cutting point.

In another preferred aspect the present invention provides a method of cutting a substrate to provide integrated circuit chips, the substrate comprising at least a semiconductor wafer, the method comprising the steps of:

guiding a beam of radiation within a controlled stream of radiation transmissive fluid to a cutting point on the substrate; removing substrate material at the cutting point by chemical etching induced by the radiation interacting with the fluid. Embodiments of the present invention in accordance with the above preferred aspects provide a means of separating integrated circuit die manufactured on a composite wafer. .

This preferred aspect of the present invention stems from the realisation that when die are manufactured on and composite wafer, the presence of the metal substrate prevents conventional means such as scribing and breaking being used to separate the individual die.

Further embodiments of the present invention provide for apparatus adapted for manufacturing semiconductor devices, said apparatus comprising: processor means adapted to operate in accordance with a predetermined instruction set, said apparatus, in conjunction with said instruction set, being adapted to perform any one or more of the method steps as disclosed herein.

Furthermore embodiments of the present invention provide for a computer program product comprising: a computer useable medium having computer readable program code and computer readable system code embodied on said medium, for manufacturing semiconductor devices, within a data processing system, said computer program product comprising: computer readable code within said computer usable medium for performing any one or more of the method steps as disclosed herein.

Other aspects and preferred aspects are disclosed in the specification and/or defined in the appended claims, forming a part of the description of the invention.

The present invention has resulted in a number of advantages such as, for example,

• Improved and more reliable base-emitter junctions for MIS transistors;

• More efficient fabricating processes are achieved by use of a selective etching process that takes advantage of the thin metal oxide insulating layer.

• The surface of a metal oxide forming a junction is protected from exposure to the atmosphere and other chemicals and the MIS junction is free from contaminants and degradation during the fabrication thereof.

• Lower turn on voltages for HBT transistors

• Higher operating frequencies • Improved manufacturability

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

Further disclosure, objects, advantages and aspects of the present application may be better understood by those skilled in the relevant art by reference to the following description of preferred embodiments taken in conjunction with the accompanying drawings, which are not shown to scale for the benefit of explanation and given by way of illustration only, and thus are not limiting to the scope of the present invention, and in which:

Figure 1 is a simplified diagram of a conventional HBT device structure; Figure 2 is a simplified diagram of an exemplary GaAs/lnGaP npn conventional HBT device;

Figure 3 is a MIS junction band diagram indicative of at least one embodiment of the present invention;

Figure 4 shows a simplified diagram of a conventional compound semiconductor MIS HBT device based on an npn GaAs structure;

Figure 4a is a bandgap diagram of a conventional GaAs based InGaP HBT device structure;

Figure 5 shows a simplified diagram of a compound semiconductor MIS HBT device structure representing a layered material arrangement in accordance with a preferred embodiment of the present invention;

Figure 6 shows a typical desired end product in respect of an exemplary MIS HBT transistor device utilising a low work function metal in an emitter structure in accordance with related art;

Figure 7 shows a composite structure formed in an intermediate process step in the fabrication of an exemplary MIS HBT transistor device in accordance with a preferred embodiment of the present invention; Figure 8 shows a composite structure formed in an intermediate process step in the fabrication of an exemplary MIS HBT transistor device in accordance with a preferred embodiment of the present invention;

Figure 9 shows a composite structure formed in a further intermediate process step in the fabrication of an exemplary MIS HBT transistor device in accordance with a preferred embodiment of the present invention;

Figure 10 shows a composite structure formed in a yet a further intermediate process step in the fabrication of an exemplary MIS HBT transistor device in accordance with a preferred embodiment of the present invention;

Figure 11a shows a band diagram of a metamorphic compound semiconductor HBT in accordance with a preferred embodiment of the present invention;

Figure 11b shows a band diagram of a metamorphic compound semiconductor HBT under active bias conditions in accordance with an embodiment of the present invention; Figure 12a shows the structure of a fabricated metamorphic HBT in accordance with an embodiment of the present invention;

Figure 12b is a bandgap diagram of a metamorphic GaAs based HBT corresponding to the structure of figure 12a in accordance with an embodiment of the present invention under active bias conditions; Figure 13 is a bandgap diagram of a metamorphic GaAs based HBT in accordance with a further embodiment of the present invention;

Figures 14a to I4e are simplified cross sectional diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing bonding layers in accordance with a preferred embodiment of the present invention; Figures 15a and 15b are further simplified cross sectional diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing bonding and adhesion layers in accordance with a preferred embodiment of the present invention;

Figures 16a to 16c are simplified cross sectional diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing patterning of epi-layers around the periphery of the composite wafer according to a preferred embodiment of the present invention;

Figures 17a to 17c are simplified cross sectional diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing a means of preventing electrolytic effects created by the presence of the metal substrate according to a preferred embodiment of the present invention;

Figure 17d is a simplified diagram of a layered device epi-layer structure in accordance with a preferred embodiment of the present invention;

Figure 18 is a simplified diagrammatic representation showing preparation of the surface of a metal substrate suitable for use in the manufacture of semiconductor devices according to a preferred embodiment of the present invention;

Figures 19a and 19b are simplified cross sectional diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing patterned bond layers according to a preferred embodiment of the present invention;

Figures 20a and 20b are simplified cross sectional diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing composition of bond layers which lower bond-related mechanical stress on the surface of the semiconductor wafer according to a preferred embodiment of the present invention;

Figures 21a and 21b are simplified cross sectional diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing composition of bond layers which improve electrical contact to the metal substrate at the bottom of via hole features in the semiconductor wafer according to a preferred embodiment of the present invention;

Figures 22a to 22c are simplified cross sectional diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing use of a planarisation technique used to improve photoresist coverage on the surface of the composite wafer after via features have been formed according to a preferred embodiment of the present invention;

Figures 23a to 23c are simplified plan view diagrams of a composite wafer suitable for use in the manufacture of semiconductor devices showing techniques for preventing unwanted thinning of photoresist after via features have been formed according to a preferred embodiment of the present invention; Figure 24 is a diagrammatic representation of the use of a laser cutting process used to separate individual chips from a composite wafer suitable for use in the manufacture of semiconductor devices according to a preferred embodiment of the present invention. DETAILED DESCRIPTION In WO 2005/022580, a MIS transistor comprising compound semiconductor material and using a rare earth oxide as the tunneliing barrier is disclosed. In particular, a MIS transistor using gadolinium oxide is disclosed.

According to a first preferred embodiment of the present invention there is provided a structure for a MIS transistor fabricated on compound semiconductor material which incorporates aluminium oxide as the insulating layer.

Aluminium oxide has a bandgap of approximately 9 eV and may form an effective barrier to hole flow in npn transistors. It is a highly chemically stable material that is able to withstand semiconductor processing chemicals and exposure to the atmosphere without degradation. The inventor has realised that these properties also mean it can form a useful tunnelling barrier in compound semiconductor MIS transistors.

In another aspect of this preferred embodiment, the present invention provides a method of fabricating a compound semiconductor MIS transistor using aluminium oxide.

As depicted in Figure 5 there is provided a metal-insulator-semiconductor transistor device structure that is based on a HBT design with a simplified tunnelling emitter structure. The emitter layer therein comprises an oxide that functions to provide a launching of free charge carriers, namely, electrons (e ^" ) into the base layer and prevents unproductive base emitter current, namely from holes, flowing from base to emitter. In this instance, the oxide layer is an insulator and the mechanism for injecting electrons (e ^' ) into the base layer of the transistor is via tunnelling, provided the oxide layer is thin enough to allow this to occur. The top semiconductor epi-layers of a conventional HBT structure's emitter are replaced with a low work function metal and insulating layer, which is preferably a metallic oxide. The choice of low work function metal in combination with the oxide layer and their respective thicknesses potentially allows injection of electrons (e ^' ) into the device at high energies and also in a highly directional fashion toward the collector, thereby optimising the electron transport through the device and consequently optimising and increasing the current gain and operating frequency of the device. As shown in Figure 5, electron (e ^" ) tunnelling in a direction normal to the plane of the oxide is more probable because the effective oxide thickness is less. Electrons (e ^" ) that attempt to tunnel through the oxide at an angle will have more oxide material to traverse and will have a correspondingly lower probability of passing through the oxide layer, ie a higher 'cross section' may be presented. Hence the thin oxide layer may act as a directional filter for electrons.

The nature of the tunnelling process through the insulating layer means that the tunnelling probability of an electron is inversely related to the exponent of the tunnelling barrier thickness and height. If the insulating layer is too thick, the tunnelling probability becomes low and the effective series resistance of the junction increases, degrading device performance. For example, the inventor has found that if the insulator is made from aluminium oxide, the layer needs to be ' made very thin (e.g. 25 angstroms) to have a high tunnelling probability and

hence low resistance at low applied voltages. At these thicknesses this represents only a few atomic layers and if there are any defects present in these layers then holes may tunnel back through the leakage path created by the defect and substantially degrade the current gain of the transistor device. Therefore, it is important to obtain a defect free oxide layer on the surface of the base layer.

The inventor has in the past used a layer of gadolinium oxide (Gd ₂ θ ₃ ) as disclosed in the above referenced PCT/AU2004/001184 in forming an oxide layer for these purposes. There are also a number of papers published on the properties of this oxide material and noting its ability to be grown in a single crystal form on GaAs, as noted above. Although this means that Gd ₂ θ ₃ is an attractive oxide to use on GaAs for MIS devices, the inventor has identified that it is relatively difficult to deposit Gd ₂ O ₃ in thin layers with no defects. One preferred method of depositing GdaG^ is to heat the material as a powder with an electron beam to the point where the material evaporates and coats a wafer. In depositing Gd ₂ Os in this way, it has been recognised that the energetic nature of the e-beam process causes source material to decompose to from a range of atomic and molecular species (such as Gd, O, Os Gd ₂ Os _? GdO etc). When this happens, oxygen diffuses away from the target wafer and Gd ₂ θ ₃ layers deposited in this fashion are typically oxygen deficient. This alters the band structure of the oxide and potentially creates broad area or localised tunnelling junction defects.

Gd2θ3 can also be deposited using sputtering techniques but deposited layers can still potentially be oxygen deficient for similar reasons.

Oxygen can be introduced into the evaporation chamber to counteract the tendency for films to become oxygen deficient, but this process is difficult to control and can potentially result in oxygen rich films, which are also undesirable. In order to overcome these difficulties in the manufacture of MIS HBTs, the inventor has realised merits of using new oxide materials and/or different deposition processes to form insulating layers with improved stoichiαmetry and minimal defects. In particular, the inventor has realised the surprising benefits of using aluminium oxide (AI ₂ O ₃ ) for the insulating layer in a MIS HBT structure. The band structure of AI ₂ O ₃ is heavily offset toward the valence band of GaAs and hence it

provides a relatively low conduction band barrier for electrons (approximately 2.8 eV) and a high valence band barrier for holes (approximately 4.8 eV). AI ₂ O ₃ also has excellent chemical stability which eases manufacturing requirements.

Other oxide materials are also potentially beneficial for MIS HBT structures for the similar reasons namely Zirconium Oxide (ZO ₂ ) and Hafnium Oxide (HfO ₂ ) having conduction band barrier heights on GaAs of approximately 1.4 and 1.5 eV respectively and valence band barrier heights of approximately 3 and 3.1 eV respectively.

In one preferred embodiment, advantage is taken from Atomic Layer Deposition (ALD) techniques, used for depositing very thin layers. The ALD process uses the self limiting nature of various gaseous chemical precursors to deposit material one atomic layer at a time. A molecule of one species is introduced into the growth chamber and reacts with the wafer surface to form a mono-layer of the species on the wafer surface. For example, in growing oxides on GaAs, water vapour is introduced into the deposition chamber and reacts with the GaAs surface to leave hydroxyl groups deposited over the surface of the wafer in the form of a continuous monolayer. Then this precursor species is removed from the chamber and a second species such as Tri-Methyl Aluminium

(TMA) is introduced. This species reacts with the first surface layer to form a monolayer of metallic oxide, in this case aluminium oxide, plus hydrogen and methane-related by-products which are extracted from the system. Then water vapour is again introduced, followed by TMA, to deposit the next oxide layer etc.

The ALD process used in this fashion produces dense defect free atomic layers. This is advantageous in the manufacture of MIS HBTs. In addition, because the oxide layers are deposited one atomic layer at a time, it is easy to control the exact thickness of the insulating layer by simply counting the number of deposition steps.

In another preferred embodiment, the invention provides another method of depositing thin, defect free insulating layers using evaporation techniques. Instead of evaporating insulating materials such as AbO ₃ ,Gd ₂ θ ₃ , Zrθ ₂ or Hfθ ₂ from oxide source material, thin layers of the corresponding metal are deposited directly on the surface of the wafer in the form of sub-layers and then exposed to

oxygen which forms the metallic oxide. The inventor has noted that the oxidization process causes the volume of the material to expand thereby placing the surface layer under substantial compressive stress. The inventor has observed that this tends to prevent voids such as pinholes forming in the layer. Reactive metals such as Al ₁ Gd, Hf and Zr readily form surface oxides on exposure to oxygen. However it may be advantageous to activate the oxygen either as plasma or as ozone to promote complete oxidation of the deposited metal. Typically, these metals will self oxidise when exposed to oxygen to a thickness of around 50 angstroms. Therefore it is advantageous to deposit the metals in layers thinner than this thickness to ensure that oxygen can penetrate to the bottom of the layer and fully form the metallic oxide. It is also advantageous to deposit a particular oxide thickness in multiple steps. For example a total oxide thickness of about 21 angstroms may be formed by depositing metal to a thickness of about 5 angstroms, oxidising this to form about 7 angstroms of oxide, and then repeating the process twice more. In this way, the metal is practically guaranteed to fully oxidise and any defects that may form in one layer are potentially covered by oxide deposited in subsequent layers.

Wafers produced by this method may typically be produced in a molecular beam epitaxy (MBE) machine so that the native semiconductor oxide on the surface of the wafers can be removed by heating in an arsenic atmosphere prior to metal sub-layer deposition and oxidisation steps.

Therefore, in accordance with at least one embodiment of the present invention there may be provided a method of manufacturing a compound semiconductor metal-insulator-semiconductor transistor device comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a collector region and a base layer coupled to the collector region; depositing at least one thin layer of a first metal over the base layer to form a base-emitter junction; exposing the thin layer of the metal to a discrete microscopic form of oxygen to form an oxide, and;

depositing a material on the thin oxide layer which is a source of free electrons.

Preferably the discrete microscopic form of oxygen comprises one of a molecular or atomic form of oxygen. Further the material that is a source of free electrons may comprise a metallic or semiconductive material, preferably a low work function metal.

The structure forming a useful device in accordance with this preferred embodiment may comprise a HBT structure forming a device that has p+ base layer, a collector layer n+ layer where the emitter is formed of a low work function metal. The oxide layer may be an Al oxide layer wherein Ai is deposited in a layer and subsequently oxidised.

In accordance with another embodiment of the present invention, the oxide layer described above may be deposited by ALD. In this case, a semiconductor wafer may be prepared with conventional subcollector, collector and base layers as would be recognised by the person skilled in the art. This wafer is then cleaned to remove any native oxide on the base layer and placed in an ALD deposition chamber. Aluminium oxide is then deposited on the wafer surface by the ALD process as noted above. The wafer may then be either taken out of the chamber so MIS emitter metal can be deposited in a separate machine or the wafer is coated with metal in the deposition in the ALD chamber by using different gaseous precursors or different growth conditions.

In yet another preferred embodiment of the invention there is provided a means of manufacturing an MIS HBT where the insulating layer in the MIS structure is protected from degradation caused by exposure to the atmosphere and processing chemicals.

Although many options are available for deposition of the low work function emitter MIS metal, the inventor has realised that that there is a significant advantage in depositing the metal in situ in either the ALD machine or the MBE (or other) machine that has deposited the oxide. The advantage is that the surface of the ^" oxide is protected from exposure to the atmosphere and other chemicals and the MIS junction is sealed and free from possible contaminants and degradation.

Irrespective of the deposition process, in a preferred embodiment, a low work function metal preferably should be deposited on the -wafer to form a tunnelling junction for an npn transistor. Although the insulating layer can be protected from possible sources of degradation by the emitter metal if it is deposited in the same process that deposits the insulator, the emitter metal itself typically has a low work function and is therefore relatively reactive and will tend to form surface oxide layers rapidly which can degrade the emitter metal or create high resistance contacts to it. The inventor has realised that the solution to this problem is to deposit not only the low work function metal but an oxide resistant capping layer as well in the same deposition process. A layer of nickel or a noble metal such as gold would be suitable for the purpose.

To manufacture the MIS transistor, the capping metal layer may be removed by a selective etching process that stops on the low work function MIS metal. For example if titanium was used as the low work function metal and this was covered with a capping layer of nickel, the nickel can be removed by nitric acid which will stop at the titanium layer.

Given that the capping layer, the emitter metal and the insulator are deposited over the entire wafer, these layers need to be patterned to form individual devices. In particular these layers need to be etched away from the surface except where the emitter of the device is to be formed.

A problem potentially is created during this etch process when these layers are etched. It is undesirable to have the edge of the metallic emitter layers coincident with or adjacent the etched edge of the insulating layer as shown in figure 6 because the electric fields are very high at this point and it is important to have a well defined surface to support this field without breaking down.

To overcome this problem the present invention provides a manufacturing process where the low work function emitter metal is exposed by removing the emitter capping metal and completely oxidises to form an additional or supplementary insulating layer at the edges of the emitter. In order to achieve this objective, the inventor has realised that the low work function metal does not need to be very thick in forming an MIS junction (e.g. only 10-20 angstroms are sufficient). This allows the metal to fully oxidise

on exposure to the atmosphere so that it forms an inert passivating layer over the surface of the wafer, except where it remains protected underneath the metal capping layer. This means that the emitter may be formed by simply etching the wafer in an etchant which selectively etches the capping layer. After this, the passivating layer may itself be removed selectively to allow other connections to be made to the transistor; preferably using photoresist means comprising masks as wouid be recognised by the person skilled in the art. With reference to Figures 6 to 10, there is shown a selective etching process that allows for a MIS transistor to be formed in accordance with this preferred embodiment of the present invention. In fabricating a MIS transistor it is preferred to form a very thin oxide layer on top of a base layer and then deposit a low work function metal on the surface of the oxide layer in a defined form as shown in Figure 6. An example metal could be Titanium (Ti) or aluminium (Al). However, the structure that is brought out of the apparatus that produces the relevant device layers is illustrated in figure 7, which shows layers that are uniform and extend across the whole wafer as there is no practical means of patterning the layers in the depositing apparatus. Therefore to form the relevant device it is necessary to etch down through the metal layer and stop at the very thin oxide layer without damaging it in any way. This is possible but requires a sophisticated approach to the selection of chemicals that will etch the metai but not harm the oxide layer. The inventor's approach in achieving the relevant etching profile is to form a transistor device not by attempting to etch through the low work function metal layer per se and stopping at the oxide layer but rather by growing a further layer of a capping metal on top of the low work function metal layer, as shown in Figure 8, that can be etched and stop at the low work function metal layer as shown in Figure 9. Once this intermediate layered material arrangement is formed the device may be formed such that the capping metal is etched to expose the low work function metal layer. Then the portion of the low work function metal that is not coated and protected by the capping metal may be exposed to an oxidising medium and form an oxide of the work function metal as shown in Figure 9. The low work function metal that is coated by the capping metal remains in its metal form. The oxide of the low work function metal may be

etched down to the base layer to allow for the connection of base contacts while masking means such as for example, photoresist protects the edges of the emitter portion of the low work function metal as shown in Figure 10.

Therefore, in accordance with this embodiment of the present invention there may be provided a method of manufacturing a compound semiconductor metal-insulator-semiconductor device comprising the steps of: providing a layered compound semiconductor material arrangement comprising at least a collector region and a base layer coupled to the collector region; depositing a thin oxide layer over the base layer; depositing a second metal layer over the thin oxide layer; depositing a capping metal layer over the first metal layer; selectively removing a portion of the capping metal layer to expose a corresponding portion of the second metal layer; forming a further oxide layer comprising an oxide of the exposed corresponding portion of the second metal layer; selectively removing a portion of the further oxide layer and corresponding portions of the thin oxide layer to expose corresponding portions of the base layer; depositing base contacts on the exposed base layer portions.

The capping metal may comprise Nickel (Ni) Gold (Au) Platinum (Pt) or other conductive materials that resist extensive oxidation and form highly conducting electrical contacts. The capping metal is also chosen to allow selective etching of this material with respect to the underlying low work function metal of the second metal layer.

The step of selectively removing a portion of the further oxide layer and corresponding portions of the thin oxide layer to expose corresponding portions of the base layer may further comprise the step of: masking at least a remaining portion of the capping metal to provide a layered structure comprising: the capping metal overlaying; the second metal overlaying;

the thin oxide overlaying; the layered compound semiconductor material arrangement. Preferably, the thin oxide layer comprises an oxide of a first metal which may be one of the following: Aluminium oxide;

Gadolinium oxide; Zirconium oxide; Hafnium oxide, or; A rare earth metal oxide. A second preferred aspect of the embodiments herein relates to what may be referred to for the purposes of this disclosure as 'metamorphic HBTs', which may be grown on a mono-crystalline substrate.

By mono-crystalline, it is meant that that a material has a specific crystal structure where atoms are arranged in regular repeating patterns and there is constant short range order and long range order of the atoms. By metamorphic, it is meant that a material deviates from an adjacent material in composition and in crystal structure or crystal lattice constant (i.e. inter-atomic spacing).

The following description uses gallium arsenide as a preferred example, but it should be realised that the present invention applies to any other compound semiconductor material structure such as those comprising indium phosphide, gallium nitride, silicon carbide and so forth.

In this preferred embodiment, a metamorphic HBT is formed by first growing sub-collector and collector layers on a mono-crystalline substrate as would be recognised by the person skilled in the art relating to fabrication of HBTs. For example, a semi-insulating GaAs wafer is placed in a growth chamber and an n+ subcollector layer is grown such that it adopts the crystal structure of the underlying substrate. Next an n-type collector layer is grown such that it also matches the same crystal structure.

In order to obtain useful material properties, it is important for compound semiconductor materials such as GaAs to be grown on substrates which have polar crystal structures. By polar crystal structures it is meant that a crystal has electro-positive components such as gallium atoms and electro-negative

components such as arsenic atoms arranged in a regular pattern. When a layer of GaAs is grown on such a polar crystal structure, the electro potential present at the surface causes gallium and arsenic atoms to bond onto the surface such that the crystal structure and its integrity is preserved. Notably, this is not the case when GaAs is grown on, for example, a material like germanium. Although the crystal lattice spacing of germanium is very close to that of GaAs, there are no localised surface potentials to form a growth template which would cause gallium and arsenic atoms to alternately arrange as the layer grows. For example two or more gallium atoms could bind to two or more adjacent germanium atoms which would then cause a crystal defect. Accordingly, GaAs layers grown on germanium tend to be amorphous which renders them insulating and of little value in conventional devices.

The inventor has recognised that the same is not necessarily true when germanium is grown on GaAs. Germanium does not need a polar crystal growth template and is able to be grown on GaAs with excellent crystal properties. Germanium atoms locate on either gallium or arsenic sites and grow in a regular, unstrained crystal pattern. It should be noted that although the crystal lattice spacing of germanium (5.658 angstroms) matches GaAs (5.653 angstroms) very closely, germanium has a tetrahedral diamond structure whereas GaAs has a zincblende interleaved face centred cubic structure.

The inventor has realised that Germanium therefore seems like an attractive choice of material for the base layer in a HBT for reasons comprising the following:

• It has a narrow bandgap (0.66eV) which will reduce turn on voltages of HBTs

• It has a hole mobility of 1900 cm ² vV ¹ which is around 5 times higher than that of GaAs and means that the resistivity of the base layer is potentially 5 times lower for the same doping density leading to improved high frequency performance. • It is chemically stable and presents opportunities of selective chemical etching relative to other semiconductor materials,

However germanium is not ordinarily used in the manufacture of GaAs based HBTs because, although the germanium base layer can be successfully grown on GaAs collector layers, the germanium base does not provide a polar growth template for overlying emitter layers and, hitherto it is not possible to grow low resistance mono-crystalline emitter layers.

Embodiments of this preferred aspect overcome this difficulty and allow low resistivity emitter layers to be formed on devices which have germanium base layers. Thereby the above mentioned benefits of germanium can be obtained in GaAs HBTs. The preferred embodiments here utilise a tunnelling emitter structure to avoid the need for crystal matching of the emitter layers. In one preferred embodiment, a tunnelling barrier layer is grown on the base layer. This barrier layer serves to block hole injection from the heavily doped base layer into the emitter. This is critical in fabricating HBTs with high current gain. The emitter barrier layer is also designed to present only a minimal (if any) barrier to electrons as they travel toward the base under conditions of forward bias.

In one embodiment, a thin layer of non-intentionally doped GaAs is grown on the transistor's germanium base layer. This layer will typically grow in an amorphous insulating state. Growth conditions may be deliberately adjusted to ensure this. For example, the growth temperature of the GaAs emitter barrier layer may be lowered to ensure the layer is amorphous and has high resistivity. Polycrystalline GaAs may also be used for this emitter barrier layer.

Next an emitter contact layer is grown on top of the emitter barrier layer. In one preferred embodiment, this layer is also amorphous or polycrystalline because there is no crystal template to grow on and is either a narrow band gap semiconductor or a metal. For example, this layer might be a binary semiconductor material such as Indium Arsenide (InAs) or gallium Antimonide

(GaSb) or a ternary compound such as Indium Gallium Arsenide (InGaAs).

Materials such as these are preferred because they have low resistivity even in an amorphous state. Alternatively this emitter contact layer could be a low work function metal such as titanium or aluminium or a semiconductor such as n+ polysilicon or n+ germanium.

The band structure of the metamorphic HBT formed in this fashion is shown in Figure 1 1b under active bias conditions. Electrons 601 ϊunne\ through the triangular potential barrier in the conduction band 602 to the base and diffuse through to the collector. The standard benefits of a tunnelling emitter structure apply in the device, namely that the electrons that reach the base are travelling in a preferred direction (filtered directionally by the barrier due to the nature of its quantum tunnelling effects) toward the collector which shortens base transit times and increases device operating speed.

An additional and unusual benefit is also obtained from this embodiment as shown in Figures 12a and 12b. At the collector base junction, germanium from the base may diffuse into the collector layer and displace gallium which would then diffuse into the base creating an inter-diffusion region 8801. Germanium is an n-type dopant in GaAs and the diffusion process will create an π+ region near the base. The band bending that occurs in this situation causes a sharp increase in the electric field in this region and creates an "electron launcher" 8802 which injects electrons at higher energy into the collector layer, thereby potentially decreasing collector transit time and increasing the F _t (where F _t is the frequency where the current gain of a HBT device drops to unity) of the device. In addition, gallium is a p-type dopant in germanium and the diffusion process also increases the base doping at the junction interface which lowers base resistance and increases device operating speed. During the manufacture of the device, heat may be applied to deliberately increase this diffusion process.

From a different perspective further embodiments of the invention provide a metamorphic HBT where the base layer is made of a graded composition material. By graded, it is meant that the atomic composition of the layer is changed during growth so that the material properties of the layer change throughout its thickness.

The collector layers of this type of metamorphic HBT are grown according to conventional industry standards, as descried above. In the case of GaAs collector layers, the base layer may be graded from GaAs to a material with a narrower bandgap such as gallium antimonide (GaSb), InGaAs or Indium Gallium Arsenide Nitride (InGaAsN). In general, binary ternary and quaternary compounds

made from Ga ₁ In, As ₁ Sb and N are ^' useful for this purpose. In particular, GaSb has a low baπdgap (0.726 eV) and an electron affinity of 4.06 eV which means that there is a minimal conduction band discontinuity with GaAs and hence minimum impediment to eiectron flow. In practice, a ternary compound GaAsSb .may be preferable to minimise the stresses and defects that occur during layer growth.

Using GaAsSb as an example, the grading of the material can either start on the base side of the base collector junction or on the collector side. The advantage of grading the material in the collector layer is that the electric field at the junction interface tends to cancel any effects associated with band bending during the transitional grading region. Figure 13 shows the band diagram of a metamorphic HBT with a GaAsSb base layer and a graded transition from GaAs to GaAsSb at the collector side of the collector base junction.

From another perspective, the choice of material for emitter tunnelling barrier is relatively broad. The example quoted previously used amorphous GaAs for the emitter barrier layer, but other amorphous materials such as gallium phosphide (GaP), InGaP or InP may be desirable as may be metallic oxides of, for example, aluminium, hafnium or zirconium. The choice of this material is driven by the conduction and valence band offsets relative to the band structure of the base \ayer. The objective is to form a relatively high barrier for holes (i.e. large valence band offset) and small barrier for electrons (small conduction band offset).

From another perspective, other embodiments of the invention provide a manufacturing method for metamorphic HBTs where the chemical properties of the base layer allow selective chemical etching of the emitter layers without effecting the base layer. In conventional GaAs InGaP HBTs, the emitter contact layers are removed with an etchant that stops at the InGaP layer, then the InGaP layer is removed with a different etchant, which does not effect the underlying base layer. A preferred embodiment provides numerous alternatives for defining selective etching processes. For example, in a device with a germanium base layer and GaAs and InGaAs emitter layers, an etchant such as citric acid can remove the emitter layers and stop at the germanium base layer.

A third aspect of preferred embodiments as described in the following detailed description may make reference to the manufacture and fabrication of gallium arsenide (GaAs) compound semiconductor devices on composite wafer assemblies or substrates. These embodiments, however, are not limited in application to GaAs and may equally apply to other semiconductor materials such as, for instance, indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC) and also silicon (Si).

In a particular embodiment, there is a means of handling semiconductor wafers while they are first thinned and then bonded to a metal substrate. Figure 14a shows a semiconductor wafer 1400 mounted on a temporary carrier substrate 1402 for thinning which is a process that would be recognised by the person skilled in the art. The adhesive bond layer 1401 is designed to be temporary and after wafers are thinned, the wafers are dismounted from the temporary carrier by softening this layer and are then diced to form chips. Figure 14b shows a thinned semiconductor wafer mounted on the temporary carrier. Typically, in conventional fabrication processes, the semiconductor wafer 1406 may be thinned down to about 50 to about 100μm. It is not normally possible to thin wafers more than this because of the difficulty of handling the wafers after they are dismounted from the temporary carrier 1402. However, in this embodiment, there is provided a semiconductor wafer mounted onto a temporary rigid carrier which is used to provide support while the fragile compound semiconductor (for example GaAs) wafer is first thinned and then bonded to a metal substrate. The 'front' side of the wafer (which is defined as the side on which epitaxial device layers are grown) is temporarily bonded to the rigid carrier and then a grinding or lapping process is applied to thin the wafer from the back. The temporary carrier may preferably comprise sapphire, for example, or some other hard supporting material like a glass. Then, with the wafer still attached to the temporary carrier, it is coated with metallic layers which are capable of forming a metallic or eutectic bond when heated in contact with metal layers deposited on the surface of the metal substrate, as described in the above referenced patents in the name of the present applicant. The thinned wafer is transferred to the metal substrate or the metal substrate is transferred to the

wafer to bond the wafer to the substrate without detaching the thinned semiconductor wafer from the temporary carrier substrate.

In more detail, with reference to Figure 14a, a temporary carrier 1402 such as sapphire is provided. A semiconductor wafer 1400, for example made from GaAs, is applied or mounted to the temporary carrier. The GaAs wafer is then thinned as shown in Figure 14b. A current industry standard is to thin GaAs wafers to approx 100μtn. However, in accordance with methods disclosed in the above referenced patents in the name of the present applicant, semiconductor wafers may be made thinner with reduced likelihood breaking because they are ultimately bonded to and supported by a substantially metallic substrate 1405 as shown in figure 14c. For example, wafers bonded to a metal substrate 1405 may be thinned to approximately 25-50μm and preferably about 25 μm. This thinner layer also facilitates heat conduction to remove heat from the wafer more efficiently. In accordance with preferred embodiments, GaAs and other semiconductor materials may be thinned to much smaller dimensions than would otherwise be achieved through the use of the temporary adhesive bond to a temporary carrier 1402.

With reference to Figure 14c, after the semiconductor wafer is thinned, a metallic bonding layer 1403 is then placed on the back side of the wafer (which is the top side of the composite wafer as shown in Figure 14c). The bond layer

1403 is designed to form a eutectic or alloyed bond to a corresponding layer 1404 deposited on the metal substrate 1405. The inventor has recognised that it is desirable to choose metals for bond layers 1404 and 1403 which form an alloy at relatively low temperatures (e.g. between about 100 and about 200 degrees Celsius) and which are then mechanically rigid at higher temperatures normally encountered in processes for fabricating devices on the composite wafer (e.g. about 400 degrees Celsius).

With reference to Figure 14c, according to an embodiment, the thinned semiconductor wafer 1400 mounted on temporary carrier 1402 is placed in a bonding machine together with metal substrate 1405 and heated to form the overall structure which is shown in Figure 14d. Bond layers 1403 and 1404 combine during the heating process to form layer 1407 which permanently bonds

the thinned semiconductor wafer to the metal substrate, thereby providing mechanical support.

At this point, the temporary carrier is removed from the composite wafer assembly to leave the structure shown in Figure 14e. In this process the semiconductor wafer is mechanically supported at all times after thinning.

In another embodiment, there is a method of bonding a semiconductor wafer to a metal substrate using a eutectic bond layer which bonds the semiconductor wafer to a metal substrate at a temperature which is low enough to prevent deterioration of the adhesive used to support the wafer on a temporary carrier.

According to a preferred embodiment, an adhesive is used to attach the semiconductor wafer to a temporary carrier while the wafer is bonded to the metal substrate. The inventor has realised that it is desirable to use organic materials such as thermoplastic compounds as the adhesive since they can be softened to facilitate removal from the composite structure after bonding by applying heat. The inventor has also realised that many organic compounds deteriorate at elevated temperatures such as those needed to form certain eutectic bonds. For example, many organic compounds deteriorate above about 200 degrees Celsius, causing them to permanently harden. The inventor has therefore realised that it is advantageous to choose metals which form eutectic bonds at temperatures well below about 200 degrees Celsius.

In addition, the inventor has realised that it is desirable for the adhesive to be viscous at the eutectic bond temperature so that it does not readily flow out from the surface of the semiconductor wafer and contaminate the bond layer or the bonding equipment. It is therefore desirable to reduce the eutectic bond temperature preferably even further than described above to prevent this problem.

With reference to Figure 14, bond layer 1407 is formed from two components 1403 and 1404.

In one embodiment, bond layer 1403 comprises an alloy formed primarily from two or more of the metals indium (In), tin (Sn), lead (Pb), silver (Ag), bismuth

(Bi) or cadmium (Cd) such that the alloy goes through a solid to liquid transition between about room temperature and about 156 degrees Celsius. For example an alloy comprising about 50% Sn and about 50% In is liquid at approximately 125 ⁰ C, and an alloy comprising about 66% Bi and about 33% Pb is liquid at approximately 70 ⁰ C.

This bond layer may be deposited as a uniform layer from a source of the specific alloy (e.g. InSn) or may be formed by sequentially depositing the component materials in a number of discrete layers. For example, In and Sn could be deposited as separate layers of In and Sn. The component materials for the bond layer 1403 are chosen also to form an alloy with bond layer 1404 which may have a much higher melting temperature. For example alloys of In, Sn and gold (Au) remain in their solid state to at least about 400 degrees Celsius. In this case, layer 1404 may be predominantly Au. It should be recognised that bond layers 1403 and 1404 are interchangeable within the scope of the present embodiment, namely that layer 1403, which is shown deposited on the surface of the semiconductor wafer can equally be deposited on the surface of the metal substrate.

The inventor has also recognised that it is advantageous to choose the composition of the low melting point layer (e.g. layer 1403 in the example of the preferred embodiment) to be resistant to surface oxidation after deposition. In this way, surface oxides do not compromise the quality of the alloy formation. For example, tin is more resistant to surface oxidation than indium. Hence it is advantageous to deposit a layer of indium first and then a layer of tin, so that surface oxidation is minimised.

Another way of preventing surface oxide formation is to cap the low melting temperature layer with a very thin layer of an inert metal such as gold. Provided this layer is thin enough and miscible with the low melting temperature alloy, it does not effect the formation of the overall bond layer. In another embodiment, there is provided a structure for supporting a semiconductor wafer on a rigid temporary carrier for thinning and subsequent bonding to a metal substrate where the adhesive used to bond the wafer to the

temporary carrier is compliant at the temperature of bonding the wafer to the substrate.

Figure 15 shows a semiconductor wafer 1500 bonded to a temporary carrier 1502 with adhesive layer 1501 and covered with bond layer 1503. Metal substrate 1505 is also shown covered with its corresponding bond layer 1504.

The inventor has realised that, although metal substrates are resilient to mechanical stress and are to some extent pliable, this lack of complete rigidity means it is difficult to ensure that their surfaces are substantially flat. As a result it is possible that the bond surface of the metal substrate may have an undulating unevenness as shown, in exaggerated form, in Figure 15. This unevenness can potentially mean that when a semiconductor wafer is bonded to the metal substrate, the force which is applied during bonding is concentrated at high points of the metal substrate surface 1507, leaving other areas uncompressed, leading to poor bond quality. In another preferred embodiment, the composition of the adhesive layer used to mount the semiconductor wafer onto the rigid temporary carrier is chosen such that it has a degree of compliance at the bond temperature, thereby partially flowing as depicted by arrows 1508 in figure 15b during bonding to distribute bond pressure evenly. If the adhesive layer is made from wax, as is the case for conventional temporary mounting methods, the wax typically melts and becomes a low viscosity liquid at bond temperatures. Because it can flow freely, it has no compliance force and it does not tend to distribute bond force evenly.

The present embodiment incorporates a thermoplastic material that preferably has a viscosity of between about 1 and about 1000 Pa.s (about 10 to about 10,000 poise) at the metallic bond alloying temperature.

In another embodiment, a plastic "double-sided" tape is used as the temporary adhesive to mount the semiconductor wafer for thinning and bonding to a metal substrate. Double-sided tapes are commonly used for attaching wafers to carrier substrates in conventional wafer tinning processes. These tapes have either thermoplastic or ultra-violet light sensitive release layers. The inventor has

realised that these tapes are useful in providing support for semiconductor wafers while they are both thinned and bonded because of the compliance of the tape material at preferred alloy bonding temperatures. This allows the compressive forces that would be experienced during bonding to be evenly distributed over the wafer surface and not restricted to the peaks or other irregularities of the wafer surface,

In another embodiment, there is a means of dressing the edge of a semiconductor wafer which is bonded to a metal substrate to eliminate the possibility of epitaxial layers on the surface of the wafer coming into electrical contact with the metal substrate.

Figure 16a shows a side view of a conventional semiconductor wafer 1601 including epi-layers 1602 on the top surface. The wafer also has rounded edges 1603 that assist in the process of spinning photoresist on the surface prior to photolithography. During the epi-growth process, epi-layers are deposited on these rounded edges 1603. This means that when wafers are thinned as shown at 1613 and mounted on metal substrates 1610 as provided according to the present embodiment, there is a possibility that these epi-layers can make electrical contact with the metal substrate or associated bond layer 1615. If this happens, an electro potential can be generated between the metal substrate and the epi-layers during aqueous processing of the composite wafer which can cause etching to be uncontrollable.

The present embodiment provides a means of preventing electro-chemical perturbation of aqueous processes by removing a portion of the semiconductor's epi-layers around the periphery of the wafer. This process is referred to as edge dressing of the wafer.

Edge dressing can be performed before the wafer is thinned and bonded to the metal substrate or afterwards. In either case, photo-resist is spun on the surface of the wafer and developed so as to expose at least a portion of the wafer around the periphery. Wet or dry etching is then used to remove the unwanted portion of the epi-layers. Preferably the epi players are removed to a depth slightly deeper than the bottom-most layer. For example, in conventional HBT epi- layers which are approximately 2 microns deep, about 3 microns of material

would be removed from the periphery of the wafer as referenced by feature 1625 in Figure 16c.

In another embodiment, there is provided a means of preventing unwanted electrolytic effects in etching processes performed on the composite wafer. As described above, electrolytic effects can arise in aqueous processing of wafers bonded to metal substrates as a result of epi-layers coming into electrical contact with the metal substrate. The inventor has realised that electrolytic effects can also occur due to bulk conductivity of the semiconductor wafer.

In a conventional GaAs semiconductor wafer, the bulk semiconductor material is not intentionally doped. However this material has an unavoidable background doping effect which leads to significant conductivity from the front side to the back side of a wafer. Most device epi-layers include a high conductivity layer which provides a conductive layer on the front of the composite wafer. The metal substrate provides a high conductivity layer on the back side of the composite wafer. In this situation, if the resistivity of the bulk material was 1 x 10 ⁷ ohm-cm, the effective resistance between these conductive layers for a 50μm thick 3 inch diameter wafer would be around 1000 ohms. For a 6 inch wafer of the same thickness this would equate to about 250 ohms. This means that a significant current can flow through the bulk wafer as a result of the electro potentials created between the metal substrate and the epi-layers.

Figure 17a shows a composite wafer placed in an aqueous etching solution as is required to manufacture semiconductor devices on the semiconductor wafer surface. The electro-potential that exists between the metal substrate 1700 and the epi-layers 1702 may cause currents 1705 to flow through the etchant solution 1706, thereby effecting the desired etching process.

The present embodiment provides a first means of preventing this electrolytic current flow by introducing an insulating layer between the semiconductor wafer and the metal substrate.

A material such as, for example, silicon nitride is deposited on either the surface of the metal substrate or the surface of the semiconductor wafer prior to bonding as shown at 1717 in Figure 17b. This layer is placed beneath the metal layer used to bond the portions of the composite wafer together as described

previously. This layer provides an insulating boundary between the epi— -layers and metal substrate and prevents electrolytic current flow, thereby restoring the etching characteristics of the epi-layers. This layer only needs to support around 1 to about 3 volts and can be relatively thin, eg about 1000 angstroms of silicon nitride is ample.

The present embodiment provides an alternate means of preventing electrolytic current flow comprising an element of the epi-layer itself.

Although it is possible to place an insulating layer between the semiconductor wafer and the metal substrate at the bond layer as shown in Figure 17b, this requires additional processing of the wafer to deposit the insulating film and to remove it when via holes are made through the semiconductor wafer to the metal substrate. Instead, in accordance with the present embodiments there is provided an insulating layer at the bottom of the epi-layer design to prevent electrolytic current flow. Figure 17c shows a composite wafer assembly including a semiconductor wafer 1723 with epi-layers 1722 and introduced insulating layer 1728. Figure 17d shows the detail of such an insulating layer. For example, in the epi-layer design for a GaAs - InGaP HBT with N+ subcollector layer, a weakly doped p-type layer is grown beneath to form a P-N junction. This junction creates a depletion region which can support the electro-potential created between the metal substrate and the surface of the epi-layers exposed to the aqueous solution. In the case of a p+ layer at the bottom of the epi-layers, an N- barrier layer would be introduced.

The advantage of this approach is that there is minimal effect to processing requirements of the semiconductor wafer and hence minimal cost increase. In another embodiment, there is provided a method of preparing a metal substrate for use in a composite wafer assembly such that the surface to be bonded is substantially very flat.

As noted in the above mentioned prior patents assigned to the present applicant, in forming composite wafer assemblies, metal substrates whose coefficient of thermal expansion (CTE) is matched to that the semiconductor wafer are used. This may restrict the choice of materials for the metal substrate.

For example, if a GaAs wafer is to be mounted to form a composite wafer, a metal substrate having a CTE of around 6.5 ppm/°C may be required,

Most metals have CTE's significantly higher than common semiconductor materials. Those that have low CTEs are typically the high melting temperature metals such as Tungsten (W), Molybdenum (Mo) and other exotic metals like Tantalum. Often, these metals do not have good thermal conductivities. In order to overcome this and to adjust the net CTE ₁ composite metals are produced such as copper-tungsten CuW and copper molybdenum (CuMo). These materials are generally formed by pressing tungsten or Molybdenum powders into prescribed shapes and then infiltrating them with liquid copper. In this way materials with composition of about 90% W and about 10% Cu can be prepared which have CTEs around 6,5ppm/°C and with attractive thermal conductivities. Preparation of these controlled expansion composites may be recognised by the person skilled in the art. However, the inventor has discovered that these conventional composite metals may be difficult to use successfully in making composite wafer assemblies because of defects found at or on the surface. These defects appear as either scratches or pits on the surface and potentially translate to voids in the bond layer of a composite wafer assembly. Pits can occur because of voids that form during the infiltration process

(e.g. during Cu infiltration of porous W structures). Pits can also be caused during the process that flattens the metal substrate surface prior to bonding. For example, it is common to flatten the surface of metal substrates using a lapping technique. In this process, lapping grit is mechanically rolled across the surface of the metal substrate, thereby causing abrasion. In the final stages of lapping, small sized grit is used to level the surface. At this stage it is possible that hard metallic particles (e.g. tungsten) can be dislodged from the relatively soft surrounding material (e.g. copper) leaving a pit in the surface and potentially creating a scratch across the surface as the dislodged particle is dragged across by the lapping motion.

The inventor realises that it is advantageous to reduce the size of particles in the metal substrate such that they are small compared to the thickness of the

bond layers used to form the composite wafer. For example, it is desirable to use bond layers of approximately 2 microns thick in bonding semiconductor wafers to metal substrates. Hence, it is advantageous to use metal substrates made from particles smaller than this dimension so that any pits created are covered by the bond layer. Typically metal substrates are currently made from particles in the range of about 5 to about 50 microns. The inventor realises that particle sizes (e.g. tungsten particles which are subsequently infiltrated with copper) should be reduced to less than about 2 microns.

In another embodiment, there is provided a method of preparing a metal substrate for use in a composite wafer assembly such that the surface to be bonded is free from significant defects.

Another embodiment relates to a process where grinding is used as the means of flattening the surface of the metal substrate. The process of grinding involves the use of a grinding wheel which has abrasive material embedded in or attached to the surface. The inventor has realised that there is a significant advantage to be gained in using a grinding process to flatten and polish the surface of metal substrates containing grains of hard metal interspersed with soft metal. The advantage is that the feed rate of the grinding wheel onto the surface can be very accurately controlled, thereby reducing stresses on the surface and minimising the likelihood of dislodging particles from the surface.

Figure 18 shows a composite metal substrate 1800 made from tungsten particles 1802 and infiltrated copper 1801. A grinding wheel 1803 is able to flatten the surface with minimal surface damage by accurately controlling the position of the grinding wheel and hence the rate of material removal. In another embodiment, there is a means of bonding semiconductor wafers to metal substrates where the bond layer is patterned to form features which improve bond uniformity, minimise the occurrence of voids in the bond layer and reduce physical stress on the semiconductor layer of the composite wafer.

When bonding a semiconductor wafer to a metal substrate to form a composite wafer, it is important to ensure that the surfaces to be bonded are in intimate contact. Otherwise it is possible that the surfaces will not bond and voids may exist between the wafer and substrate which affect the thermal, electrical

and mechanical characteristics of the composite wafer. Normally force is applied during the bond process to ensure the surfaces are in contact. However the inventor has realised that unevenness of either surface can result in high spots where bond pressure is concentrated and low spots where there is insufficient bond pressure to guarantee surface contact.

To overcome this problem, the present embodiment provides a patterned bonding layer which consists of localised areas of bonding material that tend to flow on heating to span the gap between wafer and substrate.

Figure 19a shows a preferred embodiment of the present invention where firstly a bond substrate layer 1907 is deposited on the surface of the semiconductor substrate. This material may be either a metal or a non-metal.

Next a second metal layer is deposited on top of the first layer. This layer is patterned during or after deposition using conventional shadow masking, liftoff, electroplating or etching techniques to form localised bond points 1908. Then a third metal layer 1909 is deposited over the second layer. This layer is made of the primary constituents which form a metallic bond when heated in contact with opposing bond layer 1904. The third layer is either a continuous, unbroken layer or is also patterned, as shown in Figure 19a to leave intervening gaps 1906.

For example, the first layer 1907 may be aluminium or silicon nitride, the second layer 1908 may be principally gold and the third layer 1909 may be primarily a mixture of indium and tin.

Layer 1909 is generally flat with a planar surface. During bonding, metal substrate 1905 is pressed against the surface of the semiconductor wafer such that bond layers 1904 and 1909 are generally touching. However, as noted above, these layers will not be in intimate contact everywhere on the surface and there may be areas where the two layers do not touch each other.

When the assembly is heated for bonding, bond layer 1909 becomes liquid and pulls away from layer 1907 due to the nature of the materials chosen for these layers, but remains adhered to patterned metal layer 1908. In this way, bonding "balls" 1910 are formed which draw bond material sideways toward the nucleation points 1908, and causing the balls to "reach upward" toward bond layer 1904 until they make contact and alloy with it.

This technique is similar to bump or ball bonding techniques used in the electronics industry except that here the technique has been adapted to generally form a uniform bond across an entire planar metallic surface rather than at discrete points for individual connections. By way of further example, layer 1908 may be patterned to form approximately 5 x 5 μm squares replicated on about a 20 x 20 μm grid. Bond layer 1909 may be deposited as an approximately 2 μm thick layer. When this layer melts, it will tend to flow to form spheres attached to nucleation points 1908 with diameter approximately 11 μm. However since opposing bond layer 1904 is located above the ball, a sphere will not form, and the bonding layer 1909 will be trapped in and shaped by the planar gap between the bond surfaces. The advantage of this approach is that if there was a localised unevenness on the bond surface which creates a gap of say about 10 μm in height between the bond surfaces, bond layer 1909 will "ball-up" and reach bond layer 1904, thereby bonding the surfaces together. In this way the present embodiment allows surfaces to be bonded together even though there may be localised unevennesses on the bond surfaces.

It should be recognised that providing bond layers 1907, 1908 and 1909 on the metal substrate and layer 1904 on the semiconductor wafer surface is within the scope of the present embodiment.

It should further be recognised that many other techniques can be used to form balls or other features which flow on heating to fill the gap between the bonding surfaces, and that these also are within the scope of the current embodiment. An additional feature of the present embodiments is that they can potentially provide an array of individual bond points between the bond surfaces with intervening gaps 1911 which reduce mechanical stress created at the bond surface.

The inventor has realised that bond layers formed from metals which intermix to form alloys can expand in the alloying process, thereby creating stress on the bonded surfaces. The present embodiment therefore minimises stress on the bonded surfaces, notably the semiconductor layer, by minimising the contact

area of each bond point and by providing related expansion gaps 1911 located periodically across the bond surface.

In another embodiment, there is an alternate means of reducing mechanical stress on the semiconductor layer in a composite wafer. In another embodiment, there is a bonding layer structure which prevents the alloyed bond material from coming into contact with the semiconductor layer.

As noted above, the inventor has realised that certain metals expand as they intermix to form alloys. This expansion can cause mechanical stress if it is tightly coupled to the surface of the semiconductor wafer, particularly if the semiconductor layer has been thinned significantly.

Figure 20 shows the structure of a bond layer which reduces stress caused during bonding. A first layer 2006 is deposited on semiconductor wafer 2003 as a attenuation layer which is not involved in, or inactive with respect to the bond alloying process. This layer may be made from a metal such as nickel, titanium or another material which is not physically altered by the bonding process. If this layer is made of a material such as gold, which could potentially be effected by alloying of the adjacent bond layer, barrier layer 2007 is deposited on top of this layer to isolate it from the bond alloy. The barrier layer preferably comprises a material that can withstand bonding temperatures whilst remaining inert with respect to the bonding process. Example materials for such a barrier layer may comprise SiN, SiO ₂ or other nitrides or oxides.

In either case metal layer 2004 is then deposited on top of the first 2006 or second 2007 layer. Layer 2004 is designed to alloy with layer 2005 as described previously. When the alloyed layer 2010 is formed, stresses indicated by arrows 2008 in this layer are separated from the semiconductor surface which is physically reinforced by layer 2006.

In another embodiment, there is a means of improving electrical contacts made from the semiconductor layer of the composite wafer to the underlying metal substrate.

With reference to figures 21a and 21 b, in the process of fabricating circuits on composite wafers, it is necessary to etch via holes from the surface of the

semiconductor layer 2104 to the underlying metal substrate 2100. This process may normally be performed using so called dry etching techniques where activated gasses remove semiconductor material. For example, gas mixtures of chlorine and boron tri-chloride are commonly activated to form plasmas which remove gallium arsenide material.

When the etching process reaches the metal substrate 2100, it is possible for unwanted by-products to form which create areas of high electrical resistivity. This lowers the effectiveness of via connections and degrades circuit performance. In one embodiment there is provided a structure which improves electrical connections to the metal substrate 2100 by introducing a non-passivating metal layer 2103 between the metal substrate 2100 and the semiconductor layer 2104 which is not affected by the etching process used to open vias and which does not naturally form a thick passivating oxide. This layer may be nickel, tungsten, chrome or a noble metal such as gold or platinum. If the chosen metal can potentially be effected by the bond alloy as it is formed, a barrier layer 2102 is introduced between the alloy layer 2101 and the first metal layer 2103. For example, if the first metal layer 2103 is gold, a barrier layer 2102 is provided made from a metal such as titanium which does not intermix with bond layer 2101 , as shown in Figure 21. Materials suitable for the barrier layer are as noted above.

In another embodiment, there is means of performing photolithography on the surface of a composite wafer after portions of the semiconductor wafer have been removed to expose the underlying metal substrate. When via holes are opened in the semiconductor wafer to make contacts to the underlying metal substrate, the surface topology of a composite wafer increases dramatically. The inventor has realised that this poses a problem for subsequent photolithography because of the difficulty of spinning an even layer of photoresist over the surface. In another embodiment, via holes are filled with a material such as polyimide which is spun onto the surface and patterned to fill via features, In this

way photoresist can then be spun over the surface and exposed to perform subsequent lithography.

With reference to Figure 22, via hole 2205 is opened in semiconductor wafer 2204. Then a material such as polyimide or BCB is spun onto the surface and patterned to leave the material in the via holes 2206. Then photoresist 2207 is able to be spun on the surface of the wafer for subsequent photolithography.

In another embodiment, it is advantageous to remove semiconductor material from so called "dicing lanes" on the composite wafer which are linear features where the composite wafer is ultimately divided into individual chips. It is advantageous to form these dicing lanes using the via process previously described. The inventor realises that these relatively deep via features create problems in spinning photoresist evenly over the surface of the composite wafer.

In another embodiment, dicing lanes are patterned to avoid sharp corners which create shadowing artefacts as photoresist is spun onto the surface. With reference to Figure 23a which is a plan view of a portion of the surface of a composite wafer, dicing lanes 2302 are normally formed from rectilinear features which leave rectilinear pedestals 2301 , being the chips that will be ultimately cut from the composite wafer. When photoresist 2304 is spun across the surface of the composite wafer after these pedestals have been formed, the inventor has found that it tends to pull away from the corners of the pedestals creating gaps 2305.

In another embodiment, there is a structure incorporating rounded dicing lane features 2307 around individual chip pedestals 2306 such that the photoresist spinning artefacts are avoided. The radius of curvature of these rounded comers is not critical but is preferably greater than the width of the dicing lane. It may also be preferable to provide dicing lanes in this manner where the resultant chip pedestals comprise two parallel edges or sides after the processing with the remaining sides or edges being generally curved.

In another embodiment, there is a means of separating integrated circuit die manufactured on a composite wafer.

A final process step that has to be performed on a composite' wafer involves dicing of the semiconductor wafer into individual chips. However, this poses some difficulty in composite wafers containing a metal substrate.

The inventor has realised that standard semiconductor techniques such as sawing or scribing and breaking are largely not possible with metal-backed composite wafers. The inventor has also realised that conventional laser cutting techniques which rely on ablation to remove material are also impractical because of the likely thermal damage done to adjacent semiconductor devices as the metal substrate is cut. As a further realisation, the inventor has recognised that these particular drawbacks with respect to damage of the working article during conventional cutting processes also applies to a large number of materials other than semiconductors.

US patent US4952771 entitled "Process for cutting a material by means of a laser beam" granted to Wrobel et al and incorporated herein by reference describes a water jet-guided laser cutting system where a laser beam is guided down to the cutting point by a thin jet of water. The assignee company of this US patent, namely, Synova S.A. markets a product with trademark Laser-Microjet which implements such as laser cutting process. With reference to Figure 24, a laser beam is generated by laser 2403 and guided to the cutting point by waterjet 2404 creating cutting region 2402.

The inventor has realised that the use of, for example, a controlled stream of water in this system is highly advantageous in reducing thermal damage to the material that is to be cut such as a composite wafer. In addition, the inventor has realised a subtle feature that has gone previously unnoticed in these systems, namely that chemical etching of the surface at the cutting point is a significant component of the material removal process. In this respect, it is recognised that high temperature steam (eg > about 600 ⁰ C) is highly chemically active and readily reacts with metals. The inventor considers that metallic erosion caused by exposure to high temperature steam is a significant part of the material removal process that occurs in region 2405 of Figure 24. An example described here involves a controlled stream of radiation transmissive liquid such as water, however, the inventor has recognised that the method of removing material

described and claimed herein may also be equally applicable where a controlled stream of fluid such as either a liquid or a gas is used to assist in the removal of material. Furthermore the inventor has realised that this technique may be applied to not only cutting material in general but also as a useful means of removing material in a partial sense as opposed to a complete cut through the material. As an example, the method may be applied as a means of etching a material to a controlled depth.

Thus, in another embodiment, a generic laser cutting process is provided where a laser beam is guided to a cutting point by a controlled stream of radiation transmissive liquid and where, preferably, the liquid flow rate, the liquid chemical composition and the laser power are adjusted to maximise the chemical etching of the material to be cut.

For example, the power of the laser beam can be reduced uniformly or by modulating the duty cycle to reduce thermal ablation effects and optimise chemical etching effects in the cutting process.

In another embodiment, a soluble compound can be introduced into a water supply to further enhance the laser induced etching process. The material chosen preferably does not increase the absorption of the liquid and decomposes at the cutting point to form chemical radicals which assist in material removal. For example, chlorine based salts such as sodium or potassium chloride may be used.

In another embodiment there is a means of separating chips made on a composite wafer assembly using a laser process as described above. Equally, this cutting process may be directed towards conventional Silicon based semiconductors as well as the fabrication of compound semiconductor devices.

For purposes of this disclosure, included the appended claims, the term "integrated circuit" shall be defined as a combination of interconnected circuit elements inseparably associated on or within a continuous substrate. For purposes of this disclosure, including the appended claims, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as semiconductive wafer (either alone or in assemblies comprising

other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). For purposes of this disclosure, including the appended claims, the term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.

While this invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification(s). This application is intended to cover any variations uses or adaptations of the invention following in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains and as may be applied to the essential features hereinbefore set forth.

As the present invention may be embodied in several forms without departing from the spirit of the essential characteristics of the invention, it should be understood that the above described embodiments are not to limit the present invention unless otherwise specified, but rather should be construed broadly within the spirit and scope of the invention as defined in the appended claims. Various modifications and equivalent arrangements are intended to be included within the spirit and scope of the invention and appended claims. Therefore, the specific embodiments are to be understood to be illustrative of the many ways in which the principles of the present invention may be practiced. In the following claims, means-plus-function clauses are intended to cover structures as performing the defined function and not only structural equivalents, but also equivalent structures. For example, although a nail and a screw may not be structural equivalents in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface to secure wooden parts together, in the environment of fastening wooden parts, a nail and a screw are equivalent structures.

"Comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof."