METHOD FOR MANUFACTURING DEVICE FABRICATION WAFER

Title:

METHOD FOR MANUFACTURING DEVICE FABRICATION WAFER

Document Type and Number:

WIPO Patent Application WO/2020/059810

Kind Code:

A1

Abstract:

Provided is a method for manufacturing a device fabrication wafer 43, wherein a basal plane dislocation density reduction step for reducing the density of basal plane dislocations present in a single-crystal SiC epitaxial layer 41 of a SiC epitaxial wafer 42, in which the epitaxial layer 41 is formed on a SiC wafer 40, is carried out on the SiC epitaxial wafer 42 to manufacture the device fabrication wafer 43 used for fabricating a semiconductor device. In the basal plane dislocation density reduction step, the SiC epitaxial wafer 42 is heated under the vapor pressure of Si, without forming a cap layer on the SiC epitaxial wafer 42, over a predetermined period of time required to reduce the basal plane dislocation density, thereby reducing the basal plane dislocation density while suppressing surface roughness.

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Inventors:

YABUKI NORIHITO (JP)
SAKAGUCHI TAKUYA (JP)
JINNO AKIKO (JP)
NOGAMI SATORU (JP)
KITABATAKE MAKOTO (JP)

Application Number:

PCT/JP2019/036803

Publication Date:

March 26, 2020

Filing Date:

September 19, 2019

Export Citation:

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Assignee:

TOYO TANSO CO (JP)

International Classes:

C30B29/36; C30B33/02; H01L21/265; H01L21/324

Domestic Patent References:

WO2016079984A1

2016-05-26

Foreign References:

JP2012028446A	2012-02-09
JP2014103180A	2014-06-05
JP2017517138W
JP2014101238A	2014-06-05

Other References:

T. KIMOTO ET AL.: "Fundamentals of Silicon Carbide Technology", 2014, WILEY-IEEE PRESS, pages: 201 - 203
See also references of EP 3854916A4