Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND WIRING BOARD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/042450
Kind Code:
A1
Abstract:
A purpose of the present invention is to suppress the occurrence of exposed parts on the surface of a semiconductor chip. This method for manufacturing a semiconductor device includes: preparing a semiconductor wafer on which are provided a plurality of chip regions, which are regions on which constituent elements of a semiconductor chip are already formed, and a wiring board assembly on which are provided, on a base material made of elastic material, a plurality of wiring board regions, which are regions in which a plurality of wires that electrically lead from one surface of the base material to the other surface are already formed; overlapping and joining the bottom surface of the semiconductor wafer and the wiring board assembly; cutting the semiconductor wafer so as to not divide the wiring board assembly; dicing the chip regions to make semiconductor chips, and extending the wiring board assembly in the horizontal direction to widen the gap between semiconductor chips; covering the semiconductor chips with a resin sealant while maintaining the widened state of the gap between semiconductor chips; cutting the resin sealant and the wiring board assembly between the semiconductor chips; and dicing the semiconductor device.
More Like This:
Inventors:
CHINO DAISUKE (JP)
Application Number:
PCT/JP2022/013330
Publication Date:
March 23, 2023
Filing Date:
March 23, 2022
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L23/12; H01L21/301; H01L21/3205; H01L21/56; H01L21/60; H01L21/768; H01L23/28; H01L23/522; H01L27/146
Domestic Patent References:
| WO2021111716A1 | 2021-06-10 |
Foreign References:
| JP2009267409A | 2009-11-12 | |||
| JP2010114243A | 2010-05-20 | |||
| JP2009246174A | 2009-10-22 |
Attorney, Agent or Firm:
TANAKA Hidetetsu et al. (JP)
Download PDF: