Title:
METHOD FOR SCHEDULING RETURNED DATA OF SIMT ARCHITECTURE PROCESSOR, AND CORRESPONDING PROCESSOR
Document Type and Number:
WIPO Patent Application WO/2024/045817
Kind Code:
A1
Abstract:
Provided in the present application are a method for scheduling returned data of an SIMT processor, and a corresponding processor. The method comprises: after preparing read data corresponding to memory access requests from a load/store unit of a processor, a cache memory sending to the load/store unit a notification indicating that the read data has been prepared instead of directly returning the data itself, and also locking a cache block that stores the read data; and according to the order in which the processor accesses data, the load/store unit extracting read data of a corresponding memory access request from the cache memory, and storing same in a register stack of the processor. In the solution, a load/store unit of a processor uses a data storage space of a cache memory as a temporary storage space for scheduling returned data, which adds no additional hardware costs and also improves the utilization rate of the internal storage space of the processor.
Inventors:
SU YEHUA (CN)
Application Number:
PCT/CN2023/102570
Publication Date:
March 07, 2024
Filing Date:
June 27, 2023
Export Citation:
Assignee:
HANGZHOU DENGLIN HANHAI TECH CO LTD (CN)
SHANGHAI DENGLIN TECH CO LTD (CN)
SHANGHAI DENGLIN TECH CO LTD (CN)
International Classes:
G06F9/38; G06F12/0884
Foreign References:
| CN115454502A | 2022-12-09 | |||
| CN114970848A | 2022-08-30 | |||
| CN104699631A | 2015-06-10 | |||
| CN109643443A | 2019-04-16 |
Attorney, Agent or Firm:
PANAWELL & PARTNERS, LLC (CN)
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