Title:
METHODS FOR FABRICATING A MEMORY DEVICE WITH AN ENLARGED SPACE BETWEEN NEIGHBORING BOTTOM ELECTRODES
Document Type and Number:
WIPO Patent Application WO/2016/092741
Kind Code:
A1
Abstract:
Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.
Inventors:
OKUNO JUN (US)
Application Number:
PCT/JP2015/005552
Publication Date:
June 16, 2016
Filing Date:
November 05, 2015
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
H01L27/10; H01L27/24
Foreign References:
| US20140017889A1 | 2014-01-16 | |||
| KR20100078716A | 2010-07-08 | |||
| US20130140516A1 | 2013-06-06 | |||
| US20140126265A1 | 2014-05-08 | |||
| US20100055621A1 | 2010-03-04 | |||
| JP2009099938A | 2009-05-07 | |||
| US20120302066A1 | 2012-11-29 | |||
| KR20120063390A | 2012-06-15 | |||
| US20060273456A1 | 2006-12-07 |
Other References:
None
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (Shinjuku 1-chome Shinjuku-k, Tokyo 22, JP)
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