METHODS AND SYSTEMS FOR REDUCING POWER-ON FAILURES OF INTEGRATED CIRCUITS

Title:

METHODS AND SYSTEMS FOR REDUCING POWER-ON FAILURES OF INTEGRATED CIRCUITS

Document Type and Number:

WIPO Patent Application WO2003073470

Kind Code:

A3

Abstract:

Methods and systems for protecting integrated circuits from power on sequence currents, including methods and systems for biasing transistors in paths susceptible to power-on sequence damage such that these paths do not have substantial current flow unless the power supplies controlling the gate of the susceptible transistors are powered on. In an embodiment, the invention is applied to a circuit having first and second terminals (114, 118) coupled to first and second power supplies (110, 112), respectively. The invention protects the circuit in the event that the first power supply is powered-on before the second supply.

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Inventors:

AJIT JANARDHANAN S

Application Number:

PCT/US2003/004875

Publication Date:

April 22, 2004

Filing Date:

February 21, 2003

Export Citation:

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Assignee:

BROADCOM CORP (US)

International Classes:

H03K17/0812; H03K19/00; H03K19/003; (IPC1-7): H02H7/00; H02H9/00

Foreign References:

US5717696A	1998-02-10
US4024417A	1977-05-17

Other References: